IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 72

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–32
Table 4–13. Receiver Latency
POS-PHY Level 4 MegaCore Function User Guide
128-bit shared buffer with embedded addressing
128-bit individual buffers
64-bit shared buffer with embedded addressing
64-bit individual buffers
32-bit shared buffer with embedded addressing
32-bit individual buffers
MegaCore Function
1
1
Table 4–13
Data latency:
■
■
■
■
For status latency, the values do not include waiting for the appropriate time slot in
the status channel for the status to be transmitted.
The values in
For 64- and 128-bit data path width variations, the values assume that the clock-
crossing buffer is empty. Additional latency should be added if multiple continue
traffic is expected.
The DPA adds 32 bytes for a 128-bit data path, and 16 bytes for a 64-bit data path.
For 64-bit variations using Stratix GX devices, the DPA adds an additional 24 bytes
due to the extra clocking stage with the PLL.
The external support in the shared buffer with embedded addressing mode adds
8, 4, or 2 bytes for 128-, 64-, and 32-bit data path widths, respectively.
lists the latency numbers for receiver MegaCore functions.
Table 4–13
(Bytes on SPI-4.2 Interface)
do not include the latency through the user-side buffers.
Data Latency
272
288
152
160
36
72
Chapter 4: Functional Description—Receiver
(Bytes on SPI-4.2 Interface)
Status Transmit Latency
December 2010 Altera Corporation
320
320
320
320
320
320
Latency Information