IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 139
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Appendix G: Conversion from v2.2.x
Transmitter Signals
Table G–2. Transmitter Signal Changes (Part 1 of 3)
December 2010 Altera Corporation
tdclk
tctl
tdat[15:0]
tsclk
tstat[1:0]
tsreset_n
trefclk
stat_tx_pll_locked
tdint_clk
tdint_reset_n
txsys_clk
txsys_reset_n
txreset_n
txinfo_aot[12:0]
aN_atxclk
aN_atxreset_n
aN_atxdav
aN_atxena
aN_atxdat
aN_atxsop
aN_atxeop
aN_atxmty
aN_atxerr
aN_atxadr
Version 2.4.x and 2.3.x Signal
Name
Table G–2
MegaWizard Plug-In top-level file, their equivalent v2.2.x signal names (if applicable),
and notes explaining the changes.
shows the new 2.4.x and v2.3.x transmitter signal names as they exist in the
tdclk
tctl
tdat[15:0]
tsclk
tstat[1:0]
–
trefclk
–
tx_coreclock
–
–
–
txreset_n
txinfo_aot[15:0]
aN_atxclk
aN_atxreset_n
aN_atxdav
aN_atxena
aN_atxdat
aN_atxsop
aN_atxeop
aN_atxmty
aN_atxerr
aN_atxadr
Version 2.2.x Signal Name
No change.
New. Tied high in the IP Toolbench top-level
file. Refer to
for usage.
No change.
New signal indicating PLL lock.
Derived from trefclk. Signals synchronous
to this clock are infixed by _td_.
New. Tied high in the IP Toolbench top-level
file. Refer to
for usage.
Signals synchronous to this clock are infixed
by _ty_.
New. Tied high in the IP Toolbench top-level
file. Refer to
for usage.
No change. Resets all domains.
Change in port width.
No change
POS-PHY Level 4 MegaCore Function User Guide
“Clock Structure” on page 5–8
“Clock Structure” on page 5–8
“Clock Structure” on page 5–8
Notes
G–5
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