IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 68

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–28
Table 4–9. SPI-4.2 Channel Control and Status (Part 3 of 3)
Table 4–10. DPA Control and Status
POS-PHY Level 4 MegaCore Function User Guide
rav_clk
rav_address[3:0]
rav_chipselect
rav_write
rav_read
rav_writedata[15:0]
rav_readdata[15:0]
rav_waitrequest
Note to
(1) The nominal phase offset between the clock and data is 180
err_rd_dpa
stat_rd_dpa_locked
stat_rd_dpa_lvds_locked[16:0]
ctl_rd_dpa_force_unlock
You must take into account the trace delay difference between the clock and status block, to compensate for any difference.
Table
4–9:
Signal
Signal
Input
Input
Input
Input
Input
Input
Output
Output
Direction Clock Domain
Output
Output
Output
Input
Direction
rav_clk
°
, you may want to put some timing constraints between the clock and status block.
rdint_clk
Clock Domain
Avalon-MM clock. Signals prefixed with rav_ are
synchronous to this clock. This port is absent if
asymmetric port support is turned off.
Avalon-MM address. This port is absent if asymmetric
port support is turned off.
Avalon-MM chip select. This port is absent if
asymmetric port support is turned off.
Avalon-MM write enable. This port is absent if
asymmetric port support is turned off.
Avalon-MM read enable. This port is absent if
asymmetric port support is turned off.
Avalon-MM write data. This port is absent if asymmetric
port support is turned off.
Avalon-MM write data. This port is absent if asymmetric
port support is turned off.
Avalon-MM wait request. This port is absent if
asymmetric port support is turned off.
Error flag to indicate that the DPA circuitry
could not find byte alignment. This port is
absent if DPA is turned off.
When this signal is high, it indicates that
the DPA aligner has aligned to the training
pattern. This port is absent if DPA is turned
off.
When this signal is high, it indicates that
the DPA PLL has locked. This port is absent
if DPA is turned off.
Forces the DPA circuitry and PLL to unlock
and retrain. This port is absent if DPA is
turned off.
Chapter 4: Functional Description—Receiver
Description
December 2010 Altera Corporation
Description
Signals