IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 53

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Error Flagging and Handling
Error Flagging and Handling
Figure 4–6. Example User Receiver Configuration
Note to
(1) The ctl_rd_dpa_force_unlock signal is not asserted until after start up.
(2) The delay is to ensure the ctl_rd_dpa_force_unlock signal is asserted for at least one clock cycle.
(3) The counter is intended to pulse the ctl_rd_dpa_force_unlock signal after the frame has been out of synchronization for some time.
December 2010 Altera Corporation
Figure
RSFRM Control Bit from
Atlantic Buffer Overview
Avalon Control Register
Alignment Buffer Flush
Atlantic Buffer Ready
Atlantic Buffer Reset
4–6:
DPA Force Unlock
Receiver Trained
Buffer Overflow
Send Framing
LVDS Locked
DPA Locked
DIP-4 OOS
Alignment
Asserting reset deletes all data in the buffers, and resets all state bits.
In addition to the reset, asynchronous reset and locked signals are provided for the
internal PLL, if present. The PLL should be reset and stable along with all other clocks
before the reset is released.
This section describes how the POS-PHY Level 4 receiver MegaCore function
responds to various errors.
Figure 4–6
MegaCore function.
Internal SPI-4.2 Receiver Core
shows an example user configuration for the POS-PHY Level 4 receiver
17
ctl_ry_rsfrm
ctl_rd_dpa_
force_
unlock
aN_arxreset_n
err_rd_abuf_oflw
ctl_rd_abuf_flush
Example User Side Connections
Delay
POS-PHY Level 4 MegaCore Function User Guide
Counter
stat_rd_dpa_lvds_locked
stat_rd_dpa_locked
stat_rd_rdat_sync
stat_rd_rx_dip4_oos
User Force Frame
err_ry_fifo_oflwN
User Atlantic Reset
err_rd_abuf_oflw
User Buffer Flush
4–13