IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 118

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–2
POS-PHY Level 4 MegaCore Function User Guide
1
4. Open the transmitter’s LVDS MegaWizard Plug-In and change the input clock
Figure B–2. Specify ALTLVDS Parameters
5. In the top-level design, connect the PLL reset signals (cH_rx_pll_areset and
To share a PLL between two transmitters, ensure the input frequencies are matched
and connect the trefclk signals together.
If the receiver PLL is configured as real-time configurable, it does not automatically
merge with the transmitter PLL. Use the following assignment to force the merging of
the receiver and transmitter PLLs:
set_instance_assignment -name FORCE_MERGE_PLL ON -from "<tx_pll>" -to
"<rx_pll>"
frequency to <number of Mbps>/2 (refer to
cH_tx_pll_areset) and the rdclk to the trefclk signal.
Figure
Appendix B: Sharing PLLs for Multicore Designs
B–2).
December 2010 Altera Corporation