IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 99

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Latency Information
Table 5–11. Transmitter Latency
December 2010 Altera Corporation
128-bit shared buffer with embedded addressing
128-bit individual buffers
64-bit shared buffer with embedded addressing
64-bit individual buffers
32-bit shared buffer with embedded addressing
32-bit individual buffers
MegaCore Function
Table 5–11
Data latency:
■
■
Status latency:
■
■
The values in
The external support in the shared buffer with embedded addressing mode adds
8, 4, or 2 bytes for 128-, 64-, and 32-bit data path widths, respectively.
The values do not include the time spent waiting for a complete error-free status
message. The resultant value also reflects the status channel mode—either
optimistic or pessimistic.
Turning on Lite Transmitter adds up to 32 bytes for 128-bit data path widths, or
up to 16 bytes for 64-bit data path widths.
lists the latency numbers for transmitter variations.
Table 5–11
do not include the latency through the user-side buffers.
(Bytes on SPI-4.2 Interface)
Data Latency
160
160
128
128
64
64
POS-PHY Level 4 MegaCore Function User Guide
(Bytes on SPI-4.2 Interface)
Status Receive Latency
256
256
256
256
256
256
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