IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 39

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Protocol Parameters
December 2010 Altera Corporation
f
1
1
1
The FIFO buffer threshold low (FTL) value for receiver variations controls when the
aN_arxdav signal is asserted for the read side of the FIFO buffer. If the fill level of the
buffer is higher than the FTL value, the aN_arxdav signal is asserted indicating that
there is a burst of data available.
There is no requirement to wait for the aN_arxdav signal to be asserted, you can read
from the buffer at any time.
FTL must be greater than zero.
This threshold is defined in terms of bytes, with a valid range from: N to buffer size,
in increments of N bytes, where:
■
■
■
The N-byte values for the 32-bit and 64-bit variations depend on the Atlantic interface
width. If the Atlantic interface width is greater than the data path width, the larger
value for N is used.
For the DIP-4 good and DIP-4 bad threshold values, two 4-bit inputs are associated
with the DIP-4 OOS state machine: good_level (ctl_rd_dip4_good_threshold) and
bad_level (ctl_rd_dip4_bad_threshold).
If the stat_rd_dip4_oos signal is high, and all of the DIP-4s in the control words
received in the current clock cycle (up to 8 in 128-bit mode) are good, the good counter
is incremented by 1; otherwise it is reset to 0. If the good counter reaches the
good_level threshold, the stat_rd_dip4_oos flag is cleared. A good_level of 0 is
invalid.
If the stat_rd_dip4_oos signal is low, and all of the DIP-4s in the control words
received in the current clock cycle (up to 8 in 128-bit mode) are errored, the bad
counter is incremented by 1; otherwise it is reset to 0. If the bad counter reaches the
bad_level threshold, the stat_rd_dip4_oos flag is asserted. A bad_level of 0 is
invalid.
The receiver may need to receive more control word DIP-4 errors than the DIP-4 bad
threshold parameter set in the wizard, for stat_rd_dip4_oos to go high.
For more information, refer to
Service Indication” on page
N = 4 or 8 bytes for 32-bit data path variations
N = 8 or 16 bytes for 64-bit data path variations
N = 16 bytes for 128-bit data path variations
4–18.
“DIP-4 Marking” on page 4–17
POS-PHY Level 4 MegaCore Function User Guide
and
“DIP-4 Out of
3–17