IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 114

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–4
POS-PHY Level 4 MegaCore Function User Guide
4. Data channel does not sync. This problem can be detected when
5. Data channel syncs but only training patterns are received. This problem can be
6. Receive MegaCore function detects DIP-4 errors during normal transmission. The
stat_rd_rdat_sync remains low or toggles. The following tips may prove useful:
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detected when stat_rd_rdat_sync goes high, but no data is received, and
stat_rd_tp_flag toggles. The following tips may prove useful:
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following tips may prove useful:
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altlvds_rx_component.pll_bandwidth_type = "low"
Ensure all resets are released.
Ensure all clocks are up, and measure clock frequencies.
Ensure training patterns are received.
For 128-bit receiver variations, ensure that the rxsys_clk to rdint_clk ratio is
set according to the receive clock setting in
Ensure that the calendar length and calendar multiplier are set to the same
values in both devices.
Verify timing requirements for the status channel
Select the clock edge that drives or samples the clock with ctl_ts_statedge
and ctl_rs_statedge.
Verify t
ALTDDIO megafunction keeps on-chip skew to a minimum.
Verify board skew for rsclk/rstat
Verify the setup and hold times for tstat on tsclk in the transmit MegaCore
function. The ALTDDIO megafunction keeps on-chip skew to a minimum.
Verify that tsclk is operating at the correct frequency.
The receiver MegaCore function (non-DPA variations) assume that the data is
edge aligned. The alignment can be changed at the receiver and transmitter. It
is easier to change the receiver by specifying a different alignment using the
INCLOCK_DATA_ALIGNMENT parameter of the ALTLVDS megafunction. In the
transmitter, the tdclk can be driven by a PLL clock output instead of a SERDES
data output, and the phase relation can be selected. There are notes on how to
do this in the top-level file. In either case the functional simulation models
need to be refreshed using the tool command language (Tcl) script provided.
Refer to the
for details.
This issue could be jitter related. Try adjusting the bandwidth of the PLLs. In
the fast PLLs, embedded in the ALTLVDS megafunction, this is done by adding
a pll_bandwidth_type parameter to the ALTLVDS instance. This parameter
can be low, medium, high, and defaults to auto, which should be high. The
following code is a Verilog HDL code example:
co
for the rsclk and rstat pins in the receiver MegaCore function. The
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide
Table C–1 on page
December 2010 Altera Corporation
Appendix A: Start-Up Sequence
C–1.
Troubleshooting