IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 51

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Clock Structure
Figure 4–4. Clock Layout Diagram (Full Rate)
Notes to
(1) Stratix GX 64-bit DPA only.
(2) The single clock mode removes the separate Atlantic clocks.
(3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer.
(4) The rsclk in 128-bit data path source is rdint_clk. 64-bit is internally generated (status processor).
December 2010 Altera Corporation
Figure
rsclk (Note 4)
4–4:
rdat[15:0]
rstat[1:0]
rdclk
rctl
Figure 4–4 on page 4–11
receiver MegaCore function, for 128- and 64-bit individual buffers variations. For
shared buffer with embedded addressing variations, only Atlantic buffer port 0 is
instantiated.
In 32-bit (quarter-rate) SPI-4.2 mode, all the above clocks exist. The maximum
frequency of the clocks depends on ALTDDIO_IN limitations. To minimize clock
skews, the rdclk goes into a PLL where it generates rdint_clk (×1). The PLL is
required to provide 90° phase shift, so the ALTDDIO_IN megafunction samples in the
centre of the data eye. A typical system may have a rdint_clk of 100 MHz, of which
altlvds Megafunction
LVDS
PLL
SERDES
DPA/
shows the multiple clock domain clocking structure for the
(Note 1)
Channel
EPLL
Aligner
LVTTL
LVTTL
rdint_clk
2
Processor
Processor
Status
Data
POS-PHY Level 4 MegaCore Function User Guide
Atlantic
Atlantic
Buffer N
Buffer 0
a0_arxclk
Atlantic
Interface 0
aN_arxclk
(Note 2, 3)
Atlantic
Interface N
rxsys_clk
4–11