IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 21

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Simulate the Design
December 2010 Altera Corporation
5. In Tool name, select a simulator tool from the list.
6. In the Test Benches dialog box, click New. The New Test Bench Settings dialog
7. In the New Test Bench Settings dialog box, enter the information described in
Table 2–2. NativeLink Test Bench Settings
Figure 2–2. Example of New Test Bench Settings for NativeLink
8. When you have entered the required information for your new testbench, click OK
9. Click OK in the Test Benches dialog box and then click OK in the Settings dialog
Test bench name
Top-level module in test bench
Design instance name in test bench
Run for
Test bench files
In EDA Netlist Writer options, select VHDL from the list for Format for output
netlist.
In NativeLink settings, select the Compile test bench option and then click Test
Benches. The Test Benches dialog box appears.
box appears.
Table 2–2 on page 2–5
described in the table, browse to the files in your project.
Figure 2–2 on page 2–5
<variation_name> is example.
in the New Test Bench Settings dialog box.
box.
Parameter
(refer also to
shows an example of the testbench settings when the
Figure 2–2 on page
<any name>
tb
<variation name>
100 ns
<variation name>_tb.v
POS-PHY Level 4 MegaCore Function User Guide
Setting and File Name
2–5). To enter the files
2–5