IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 104

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–4
Table 6–3. Error Generation Tasks in the Packet Generation Module
POS-PHY Level 4 MegaCore Function User Guide
spi_gen.pkt2
(port,err,size,pkt_num)
spi_gen.cw
(word[15:0],dip4err)
Task Format
1
To simulate errors using these tasks, you must turn on dynamic phase alignment
(DPA) and Atlantic error checking when parameterizing your MegaCore function.
Sends a single packet
and can optionally
insert various
protocol errors.
Sends a control word
for one clock cycle.
The DIP4 is auto
calculated and
inserted into word
[3:0]. The DIP4
calculation can be
inverted.
General Description
port[7:0] sets the port address (ADR bits [11:4] of SOP
control word).
err sets the error code for inserting various protocol
errors into the SPI-4 stream. The error codes are:
■
■
■
■
■
■
■
■
■
■
All other values are undefined.
size sets the length field of the packet header.
pkt_num[7:0]sets the value of the first byte after the
header. This byte is then incremented for the rest of the
packet.
word[15:0]is the control word to be inserted.
When the dip4err bit is set, the DIP4 calculation is
inverted.
0 = no error
1 = invert DIP4 and set error bit
2 = omit start of packet (SOP)
3 = omit end of packet (EOP)
4 = insert a payload control word mid-packet (not really
an error)
5 = insert an idle followed by a payload control word
mid-packet (not really an error)
6 = set SOP in idle EOP (odd or even) control word
following packet
7 = set SOP in idle EOP (abort) control word following
packet
8 = set EOP (abort) for packet and insert error bit in
header
9 = invert dip4 but do not set error bit
Input Parameters Description
December 2010 Altera Corporation
Receiver Testbench Examples
Chapter 6: Testbench