IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 81

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Clock Structure
Table 5–1. Clock Domains
December 2010 Altera Corporation
Transmit MegaCore function
clock (trefclk/tdint_clk)
Transmit status channel
clock (tsclk)
System clock (txsys_clk)
Transmit Atlantic clock
(aN_atxclk)
Clock Domain
Multiple Clock Domain
In multiple clock domain mode, the tdint_clk clocks the protocol logic of the
MegaCore function, and the read side of the Atlantic FIFO buffers.
In multiple clock mode, an extra input clock is instantiated for each Atlantic FIFO
buffer in the MegaCore function, which is used for the write side of the buffers. The
naming convention for these input clocks is aN_atxclk. These clocks are inputs to the
MegaCore function and can either be tied together or controlled individually.
Table 5–1
bus.
The trefclk clock is the input to the MegaCore function. The tdint_clk clock is an output
wire, and is the output of a fast PLL. The trefclk can be generated from multiple possible
sources, for various frequencies. For example, a SPI-4.2 bus rate of 800 Mbps requires a
100 MHz clock for a data path width of 128 bits, a 400 MHz clock for a data path width of 32
bits, and a 200 MHz clock for a data path width of 64 bits.
The SPI-4.2 specification specifies a maximum status clock of ¼ of the tdclk frequency.
This clock may be independent of tdclk. For example, it is possible to have a frequency of
100 MHz or less for a data path width of 128 or 64 bits, and of 25 MHz or less for a data path
width of 32 bits.
The txsys_clk frequency must be faster than, or equal to, the tsclk frequency. This clock
transfers status to the external status interface.
This clock is typically asynchronous to trefclk, but this is not a restriction. In the
individual buffers mode, there may be as many clock domains as there are ports, and they
are all allowed to be of different phase and frequency.
shows the clock frequency values for a data rate of 800 Mbps on the SPI-4.2
Description
POS-PHY Level 4 MegaCore Function User Guide
5–9