cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 105

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PIC Functional Description
4.8.2
For each of 16 input IGs of four signals each (except IG0
and IG2 with two signals each), XPIC provides a four input
“OR”. Thus, 16 outputs are formed. A software readable
XPIC Input Request Register (XIRR) is available to read
the status of the 64 inputs. Outputs [0:1] and [3:15] are
connected directly to the corresponding inputs on LPIC.
Output 2 can be used as an ASMI.
4.8.3
The LPIC consists of two 8259A compatible Programmable
Interrupt Controllers (PICs) connected in Cascade mode
through interrupt signal two (see Figure 4-19). LPIC con-
tains mechanisms to:
1)
Unrestricted Z
Input 0
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
Input 8
Input 9
Input 10
Input 11
Input 12
Input 13
Input 14
Input 15
Note: Cascading the 8259A PICs. The INT output of the slave is connected to the IRQ2 input of the master.
Mask any of the 15 inputs via an Interrupt Mask Regis-
ter (IMR).
Extended PIC (XPIC)
Legacy PIC (LPIC)
IRQ8
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
Source
MFGPT_Comp_1A
MFGPT_Comp_1B
MFGPT_Comp_1C
MFGPT_Comp_1D
MFGPT_Comp_2A
MFGPT_Comp_2B
MFGPT_Comp_2C
MFGPT_Comp_2D
GPIO Interrupt 0
GPIO Interrupt 1
GPIO Interrupt 2
GPIO Interrupt 3
GPIO Interrupt 4
GPIO Interrupt 5
GPIO Interrupt 6
GPIO Interrupt 7
IRQ9
D0-D7
IRQ10
Table 4-14. IRQ Map - Unrestricted Sources Z
8259A Slave
IRQ11
Figure 4-19. Cascading 8259As for LPIC
(Continued)
IRQ12
IRQ13
INTA
IRQ14
INT
IRQ15
Comment
OR of MFGPT_Comp_1 0 and 4.
OR of MFGPT_Comp_1 1 and 5.
OR of MFGPT_Comp_1 2 and 6.
OR of MFGPT_Comp_1 3 and 7.
OR of MFGPT_Comp_2 0 and 4.
OR of MFGPT_Comp_2 1 and 5.
OR of MFGPT_Comp_2 2 and 6.
OR of MFGPT_Comp_2 3 and 7.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
From GPIO Interrupt/PME Mapper.
105
2)
3)
4)
5)
In addition to the above 8259A features, there are two reg-
isters to control edge/level mode for each of the interrupt
inputs as well as shadow registers to obtain the values of
legacy 8259A registers that have not been historically
readable.
Determine the input request status via an Interrupt
Request Register (IRR).
Generate an interrupt request (INTR) to the processor
when any of the unmasked requests are asserted.
Provide an interrupt vector to the processor as part of
an interrupt acknowledge operation based on request
priorities.
Determine which requests are acknowledged but not
yet fully serviced, via an In-Service Register (ISR).
IRQ0
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
IRQ1
D0-D7
IRQ2
8259A Master
IRQ3
IRQ4
IRQ5
INTA
IRQ6
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INT
IRQ7