cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 134

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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4.13 LOW PIN COUNT PORT
The Low Pin Count port is based on Intel’s Low Pin Count
(LPC) Interface Specification v1.0. In addition to the
required pins, the CS5535 also supports two optional pins:
LDRQ# and SERIRQ. The LPC interface supports memory,
I/O, DMA, and Intel’s Firmware Hub Interface. Figure 4-38
shows the block diagram of the LPC port.
Features
• Based on Intel’s Low Pin Count (LPC) Specification
• Serial IRQ support.
• Supports memory, I/O, and DMA cycle types.
v1.0.
To PIC
LPC Master
Local Bus Master
Local Bus Slave
SIRQ
LDRQ
DRQ
LPC Reg
LPC to/from Local Bus
Busy
Busy
Local Bus Slave
Initiates all transactions on LPC bus, takes/issues requests from Local bus.
Takes request from LPC master and DMA.
Issues request to LPC master from Local bus.
Decodes SERIRQ into IRQ to be passed on to PIC.
Decodes LDRQ# into DRQ sets and clears.
Combines multiple LDRQ# outputs and passes results to DMA.
Contains all the LPC I/O registers.
LPC to Local bus interface module.
Generates busy signal for clock controls.
SERIRQ
SIRQ
LPC Reg
Figure 4-38. LPC Block Diagram
LPC to/from Local Bus
LFRAME#
GeodeLink Adapter
LPC Master
Local Bus
134
LAD[3:0]
• Bus master cycles not supported.
• CLKRUN# and LPCPD# not supported. SMI# and PME#
• On-chip DMA transfers through LPC.
• Supports Intel’s FirmWare Hub (FWH) Interface:
supported via GPIOs.
— 5 Signal communication interface supporting byte-at-
— LAD[3:0] called as FWH0-FWH3 and LFRAME# as
a-time reads and writes.
FWH4.
Local Bus Master
LDRQ#
LDRQ
DRQ
From DMA
To DMA
Revision 0.8