cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 241

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
ACC Register Descriptions
5.3.2.5
ACC I/O Offset
Type
Reset Value
15
15:10
Bit
9
8
7
6
5
4
3
2
1
0
14
Second Level Audio IRQ Status Register (ACC_IRQ_STATUS)
Name
RSVD
BM7_IRQ_STS
BM6_IRQ_STS
BM5_IRQ_STS
BM4_IRQ_STS
BM3_IRQ_STS
BM2_IRQ_STS
BM1_IRQ_STS
BM0_IRQ_STS
WU_IRQ_STS
IRQ_STS
13
12h
RO
00000000h
RSVD
12
11
Description
Reserved. Reads return 0.
Audio Bus Master 7 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 7. Reading the Bus Master 7 IRQ Status
Register clears this bit.
Audio Bus Master 6 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 6. Reading the Bus Master 6 IRQ Status
Register clears this bit.
Audio Bus Master 5 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 5. Reading the Bus Master 5 IRQ Status
Register clears this bit.
Audio Bus Master 4 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 4. Reading the Bus Master 4 IRQ Status
Register clears this bit.
Audio Bus Master 3 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 3. Reading the Bus Master 3 IRQ Status
Register clears this bit.
Audio Bus Master 2 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 2. Reading the Bus Master 2 IRQ Status
Register clears this bit.
Audio Bus Master 1 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 1. Reading the Bus Master 1 IRQ Status
Register clears this bit.
Audio Bus Master 0 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 0. Reading the Bus Master 0 IRQ Status
Register clears this bit.
Codec GPIO Wakeup IRQ Status. If this bit is set, it indicates that an IRQ was caused
by a GPIO Wakeup Interrupt event (serial data in going high during power-down).
Reading the Codec GPIO Status Register clears this bit.
Codec GPIO IRQ Status. If this bit is set, it indicates that an IRQ was caused by a
GPIO event in the AC97 Codec (slot 12, bit 0). Reading the Codec GPIO Status Regis-
ter clears this bit.
(Continued)
ACC_IRQ_STATUS Bit Descriptions
10
ACC_IRQ_STATUS Register Map
9
8
241
7
6
5
4
3
2
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