cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 466

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

www.national.com
5.17 MULTI-FUNCTION GENERAL PURPOSE TIMER REGISTER DESCRIPTIONS
The registers for the Multi-Function General Purpose Timer
(MFGPT) are divided into three sets:
• Standard GeodeLink Device MSRs (Shared with DIVIL,
• MFGPT Specific MSRs
• MFGPT Native Registers.
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 3.2 "CS5535
MSR Addressing" on page 53 for more details on MSR
addressing.
MSR Address
I/O Offset
see Section 5.6.1 on page 299.)
MFGPT
5140002Ah
5140002Bh
51400028h
51400029h
0Ch
1Ch
0Ah
0Eh
1Ah
1Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
18h
20h
22h
24h
26h
28h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
WO
Width
(Bits)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Register Name
MFGPT NMI and Reset Mask (MFGPT_NR)
MFGPT Reserved (MFGPT_RSVD)
MFGPT IRQ Mask (MFGPT_IRQ)
MFGPT Clear Setup Test (MFGPT_SETUP)
Table 5-65. MFGPT Native Registers Summary
Table 5-64. MFGPT Specific MSRs Summary
Register Name
MFGPT0 Comparator 1 (MFGPT0_CMP1)
MFGPT0 Comparator 2 (MFGPT0_CMP2)
MFGPT0 Up Counter (MFGPT0_CNT)
MFPGT0 Setup (MFGPT0_SETUP)
MFGPT1 Comparator 1 (MFGPT1_CMP1)
MFGPT1 Comparator 2 (MFGPT1_CMP2)
MFGPT1 Up Counter (MFGPT1_CNT)
MFPGT1 Setup (MFGPT1_SETUP)
MFGPT2 Comparator 1 (MFGPT2_CMP1)
MFGPT2 Comparator 2 (MFGPT2_CMP2)
MFGPT2 Up Counter (MFGPT2_CNT)
MFPGT2 Setup (MFGPT2_SETUP)
MFGPT3 Comparator 1 (MFGPT3_CMP1)
MFGPT3 Comparator 2 (MFGPT3_CMP2)
MFGPT3 Up Counter (MFGPT3_CNT)
MFPGT3 Setup (MFGPT3_SETUP)
MFGPT4 Comparator 1 (MFGPT4_CMP1)
MFGPT4 Comparator 2 (MFGPT4_CMP2)
MFGPT4 Up Counter (MFGPT4_CNT)
MFPGT4 Setup (MFGPT4_SETUP)
MFGPT5 Comparator 1 (MFGPT5_CMP1)
466
All MSRs are 64 bits, however, the MFGPT Specific MSRs
(summarized in Table 5-64) are called out as 32 bits. The
MFGPT module treats writes to the upper 32 bits (i.e., bits
[63:32]) of the 64-bit MSRs as don’t cares and always
returns 0 on these bits.
The Native registers associated with the MFGPT (summa-
rized in Table 5-65) are accessed via a Base Address Reg-
ister, MSR_LBAR_MFGPT (MSR 5140000Dh), as I/O
Offsets. (See Section 5.6.2.6 on page 311 for bit descrip-
tions of the Base Address Register.)
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
Reset Value
00000000h
00000000h
00000000h
00000000h
Reset Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Reference
Reference
Page 467
Page 469
Page 471
Page 471
Page 472
Page 473
Page 474
Page 475
Page 472
Page 473
Page 474
Page 475
Page 472
Page 473
Page 474
Page 475
Page 472
Page 473
Page 474
Page 475
Page 472
Page 473
Page 474
Page 475
Page 472
Revision 0.8