cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 137

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
LPC Port Functional Description
4.13.2 Cycle Protocol
Start of Cycle (see Figure 4-39): The host asserts
LFRAME# for one or more clocks and drives a START
value on LAD[3:0], all peripherals stop driving the LAD[3:0]
signals even if in the middle of a transfer. The peripheral
must always use the last START value when LFRAME#
was active. On the clock after the START value, the host
de-asserts LFRAME#.
Field
SYNC
LFRAME#
LAD[3:0]#
LFRAME#
LAD[3:0]#
Table 4-23. Cycle Field Definitions: Target Memory, I/O, and DMA (Continued)
LCLK
LCLK
# Clocks
1-N
START CYCTYP
Figure 4-40. Abort Mechanism Timing Diagram
START CYCTYP
1
Figure 4-39. Start of Cycle Timing Diagram
1
Comment
Sync: Allows peripheral or host to synchronize (add wait-states). Generally, the peripheral or
host drives 0101 or 0110 until no more wait-states are needed. At that point it will drive 0000. All
other combinations are reserved.
0000 Sync achieved with no error.
0101 Indicates that Sync not achieved yet, but the part is driving the bus.
0110 Indicates that Sync not achieved yet, but the part is driving the bus, and expect long
1010 Special case. Peripheral indicating errors, see sync section in protocol overview.
1001 DMA (only). Sync achieved with no error and more DMA transfer desired to continue
DMA. Sync achieved with no error. Also indicates no more transfer desired for that chan-
nel, and DMA request is de-asserted.
DMA. Part indicating wait states.
Sync.
DMA. Part indicating wait states, and many wait states will be added.
DMA. Sync achieved with error. Also indicates no more transfers desired for that chan-
nel, and DMA request is de-asserted.
after this transfer.
1
1
(Continued)
ADDR
ADDR
1 - 8
1 - 8
137
TAR
TAR
2
2
Abort Mechanism (see Figure 4-40): The host can cause
an abort on the LPC interface by driving LFRAME# active
with a START value of 1111b. The host must keep
LFRAME# active for at least four consecutive clocks and
drive LAD[3:0] to 1111b no later than the fourth clock after
LFRAME# goes active. The host must drive LFRAME#
inactive for at least one clock after an abort.
An abort typically occurs on SYNC timeouts.
Too many
Syncs causes
Timeout
SYNC
SYNC
1 - n
DATA
2
Peripheral must
Stop driving
TAR
2
START
Chip set will
drive high
1
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