cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 170

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Flash Controller Functional Description
4.18.1.3 NAND ECC Control Module
The NAND ECC Control Module is part of the NAND Flash
Controller. It calculates 22-bit ECC parity for each of the
256 bytes of the NAND Flash’s data transferred on the
Local bus. The ECC calculation algorithm follows the
SmartMedia Physical Format Specification. The ECC algo-
rithm is capable of single-bit correction and 2-bit random-
error detection. ECCs are generated only for data areas
and no ECC is generated for page-data redundant areas
containing ECCs as the page-data redundant area is dupli-
cated for reliability. For ECC calculations, 256 bytes are
handled as a stream of 2048-bit serial data. In the event of
an error, the error-correction feature can detect the bit loca-
tion of the error based on the results of a parity check and
correct the data.
Hardware Operation
The ECC engine treats 256-byte data as a block. Each byte
has an 8-bit address called a Line Address (LA). Each bit in
a byte has a 3-bit address called a Column Address (CA).
Combining these two address fields forms an 11-bit unique
R/B#
WE#
CLE
CE#
RE#
ALE
I/O
00h
CA
Figure 4-56. Flash Controller NAND Read Cycle
PA0
PA1
PA2
(Continued)
170
address for every single bit in the 256-byte data block. The
address uses the notation: LLLL_LLLL, CCC. This module
contains an 8-bit counter to keep track of the LA of each
byte. Each ECC parity bit calculation in the ECC engine
produces even parity of half of the data bits in the block.
Different parity bits use different sets of the bits. For exam-
ple, CP0 is the even parity bit of the bits with Column
Address bit 0 equals 0. CP1 is the even parity bit of the bits
with Column Address bit 0 equals 1. Both odd and even
parity are supported for ECC. The ECC parity available in
the NAND ECC column, LSB line, and MSB line parity reg-
isters is the inverted output of the ECC parity from the ECC
engine in the case of odd ECC parity and the non-inverted
output in the case of even parity. Table 4-36 lists the rela-
tionship between the parity bits and the corresponding bit
addresses. The hardware ECC engine calculates 22-bit
ECC parity whenever there is a data write or data read
to/from the NAND Flash device. On power-up, the ECC
engine is configured to be odd parity. Even or odd ECC
parity is controlled by bit 2 of NAND ECC Control register
(Flash Memory Offset 815h).
D0
D1
D2
(n-1)
D
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