cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 76

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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4.2
The GeodeLink PCI Bus South Bridge (GLPCI_SB) pro-
vides a PCI interface for GeodeLink Device based designs.
Its three major functions are:
1)
2)
3)
Features include:
• PCI v2.2 compliance. Optional signals PERR#, SERR#,
• 32-bit, 66 MHz PCI bus operation and 64-bit, 66 MHz
• Target support for fast back-to-back transactions.
• Zero wait state operation within a PCI burst.
• MSR access mailbox in PCI configuration space.
• Capable of handling in-bound transactions after
• Dynamic clock stop/start support for GeodeLink and PCI
LOCK#, and CLKRUN are not implemented.
GeodeLink Device operation.
RESET_OUT# + 2 clock cycles.
clock domains via power management features.
Acting as a PCI slave and transforming PCI transac-
tions to GLIU transactions as a GLIU master.
Acting as a GLIU slave and transforming GLIU trans-
actions to PCI bus transactions as a PCI master.
Providing a CPU serial interface that conveys system
information such as interrupts, SSMI, ASMI, etc.
GEODELINK PCI SOUTH BRIDGE
REQ# / GNT#
MSR
Figure 4-2. GLPCI_SB Block Diagram
Request
Transaction Forwarding
FIFOs/Synchronization
GeodeLink Interface
PCI Bus Interface
Data
76
• Programmable IDSEL selection.
• Support active decoding for Legacy I/O space 000h to
• Support subtractive decode for memory and I/O space.
• Special performance enhancements for fast IDE PIO
The GLPCI_SB module is composed of the following major
blocks:
• GeodeLink Interface
• FIFO/Synchronization
• Transaction Forwarding
• PCI Bus Interface
• CPU Interface Serial (CIS)
The GLIU and PCI bus interfaces provide adaptation to the
respective buses. The Transaction Forwarding block pro-
vides bridging logic. The CIS block provides serial output to
the CPU for any change in SSMI and the selected side-
band signals. Little endian byte ordering is used on all sig-
nal buses.
Figure 4-2 is a block diagram of the GLPCI_SB module.
3FFh and DMA High Page 480h to 48Fh.
data transfers.
Request
GX2 CIS
CIS
PCI Bus
Side-band signals
Revision 0.8