cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 323

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
5.8
The registers for the Programmable Interval Timer (PIT)
are divided into three sets:
• Standard GeodeLink Device MSRs (Shared with DIVIL,
• PIT Specific MSRs
• PIT Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 3.2 "CS5535
MSR Addressing" on page 53 for more details on MSR
addressing.
MSR Address
see Section 5.6.1 on page 299.)
I/O Address
51400036h
51400037h
PROGRAMMABLE INTERVAL TIMER REGISTER DESCRIPTIONS
40h
41h
42h
43h
61h
Type
Type
R/W
R/W
R/W
RO
W
W
W
R
R
R
Register Name
PIT Count Enable (PIT_CNTRL)
PIT Shadow (PIT_SHDW)
Width
(Bits)
8
8
8
8
8
8
8
8
Table 5-21. PIT Native Registers Summary
Table 5-20. PIT Specific MSRs Summary
Register Name
PIT Timer 0 Counter - System
(PIT_TMR0_CNTR_SYS)
PIT Timer 0 Status - System
(PIT_TMR0_STS_SYS)
PIT Timer 1 Counter - Refresh
(PIT_TMR1_CNTR_RFSH)
PIT Timer 1 Status - Refresh
(PIT_TMR1_STS_RFSH)
PIT Timer 2 Counter - Speaker
(PIT_TMR2_CNTR_SPKR)
PIT Timer 2 Status - Speaker
(PIT_TMR2_STS_SPKR)
PIT Mode Control Word
(PIT_MODECTL_WORD)
Port B Control (PIT_PORTBCTL)
323
All MSRs are 64 bits, however, the PIT Specific MSRs are
called out as 8 bits. The PIT treats writes to the upper 56
bits (i.e., bits [63:8]) of the 64-bit MSRs as don’t cares and
always returns 0 on these bits. The PIT Specific MSRs are
summarized in Table 5-20.
The Native registers associated with the PIT are summa-
rized in Table 5-21 and are accessed as I/O Addresses.
The reference column in the tables point to the page where
the register maps and bit descriptions are listed.
Reset Value
Reset Value
00h
03h
00h
00h
00h
00h
00h
00h
00h
00h
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