cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 359

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
SMB Controller Register Descriptions
5.11.1.6
SMB I/O Offset
Type
Reset Value
This register enables/disables the functional block and determines the SMB clock rate.
5.11.1.7
SMB I/O Offset
Type
Reset Value
This register enables/disables the functional block and determines the SMB clock rate.
SCLFRQ
SCLFRQ
Bit
6:0
Bit
7:0
7
7
7
SMB Control 2 (SMB_CTRL2)
SMB Control 3 (SMB_CTRL3)
Name
SCLFRQ
EN
Name
SCLFRQ
05h
R/W
00h
06h
R/W
00h
6
6
Description
SMB_CLK Frequency. This field along with SMBCTL3 defines the SMB_CLK period
(low and high time) when the device serves as a bus master. The clock low and high
times are defined as follows:
t
where t
SCLFRQ can be programmed to values in the range of 00010002 (8
11111112 (127
The low and high time are generally equal unless two or more devices are driving the
SCL line.
Enable.
0: SMB is disabled, all registers are cleared, and clocks are halted. In the SMBCST
1: SMB is enabled.
Description
SMB_CLK Frequency. This field along with SMBCTL2.SCLFRQ defines the
SMB_CLK period (low and high time) when the device serves as a bus master. The
clock low and high times are defined as follows:
t
where t
The highest value that can be programmed into these two registers for lowest fre-
quency is FFFFh and the lowest value is 0008h.
SCLl
SCLl
register all bits are cleared except the TSDA bit, it reflects the value of SMB_DATA.
5
5
= t
= t
CLK
CLK
SCLh
SCLh
SMB_CTRL2 Bit Descriptions
SMB_CTRL3 Bit Descriptions
SMB_CTRL2 Register Map
SMB_CTRL3 Register Map
is the module input clock cycle.
is the module input clock cycle.
= 2*SCLFRQ*t
= 2*SCLFRQ*t
10
). Using any other value has unpredictable results.
4
4
(Continued)
359
CLK
CLK
EN
EN
3
3
2
2
1
1
10
) through
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0