cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 178

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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4.20 TAP CONTROLLER
The TAP Controller is IEEE 1149.1 compliant. A block dia-
gram of the TAP, boundary scan and Internal scan is shown
in Figure 4-63. The JTAG pins TCK, TDI, TDO, TMS, and
RESET_STAND# are directly supported. The TAP is pro-
grammable by means of TAP control instructions. The
meanings of the various instructions are shown in Table 4-
38 on page 179 along with the length of the DR (Data reg-
ister) that can be accessed once the instruction is entered.
All Data registers shift in and out data LSB first. The
Instruction register and all Data registers are shift registers,
so if more bits are shifted in than the register can hold, only
the last bits shifted in - the MSBs - will be used. This can be
useful on systems that always shift in a multiple of 8 bits to
the Data or Instruction registers. The Instruction register is
24 bits wide and defined in Table 4-39 on page 180.
The TAP Controller can be initialized synchronously or
asynchronously. For a synchronous reset, holding TMS
high and clocking TCK a minimum of five times will put the
TAP state machine into the Test-Logic-Reset state. Asyn-
chronous
RESET_STAND# (Tap Controller Reset) (see Section 3.6
"Reset
RESET_STAND#, the TAP state machine will immediately
enter the Test-Logic-Reset state.
RESET_STAND# or
LVD Standby Reset
Considerations"
reset
TDO
TMS
TCK
is
Memory BIST Interface
TDI
available
Figure 4-63. TAP Controller, Boundary Scan Block Diagram
on
To Bscan
page
too
by
58).
asserting
To Iscan
From
178
Internal Scan Registers
Boundary Scan Registers
The TAP has specific pre-assigned meanings to the bits in
the 24-bit IR register. The meanings are summarized in
Table 4-39. Note that the bits only affect the chip once the
“Update-IR” JTAG state occurs in the JTAG Controller -
shifting through these bits will not change the state of inter-
nal signals (e.g., test_mode). The details on JTAG Control-
ler states are covered in the IEEE 1149.1 standard.
Features
TAP control/access to the following:
• Shift/capture of CCU scan chain
• GLIU access via Request-in, Request-out packets
• TAPSCAN access
• TRI-STATE mode control
• Memory BIST control
• ID code
• Configures component for JTAG bypass mode
TAP
Serial Interface with GLCP
From Iscan
From Bscan
Revision 0.8