cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 343

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PIC Register Descriptions
5.9.2.8
I/O Port
Type
Reset Value
Bit
7:5
4:3
2:0
Bit
6:5
4:3
RSVD
7
2
7
Operation Command Word 3 (PIC_OCW3)
Name
ROT_EOI
00
IRQ
Name
RSVD
SP_MASK
01
RSVD
Master: 020h
Slave:
6
SP_MASK
0A0h
WO
00h
Description
Rotate/EOI Codes.
000: Clear rotate in Auto EOI mode.
100: Set rotate in Auto EOI mode.
001: Non-specific EOI.
101: Rotate on non-specific EOI command.
010: No operation.
110: Set priority command (bits [2:0] must be valid).
011: Specific EOI (bits [2:0] must be valid.
111: Rotate on specific EOI command (bits [2:0] must be valid)
Write to 0. Write to 00 to write OCW2 (rather than OCW3 or ICW1). (See Section 5.9.2
"PIC Native Registers" on page 339.)
IRQ Number (000-111).
Description
Reserved. Write to 0.
Special Mask Mode. The internal SMM Mode bit can be set or cleared using this 2-bit
field.
0x: No change to the internal SMM Mode bit.
10: Clears the internal SMM Mode bit (i.e., value of SMM Mode bit = 0). (Default after
11: Sets the internal SMM Mode bit (i.e., value of SMM Mode bit = 1).
While the internal SMM Mode bit is 1, interrupt blocking by priority is disabled, and only
the Interrupt Mask Register (OCW1) is used to block interrupt requests to the CPU.
While the internal SMM Mode bit is 0 (the default), an unmasked IRQ must also be of
higher priority than the IRQ of the currently running interrupt service routine. Regard-
less of the setting of this bit, the IRQ priority is still used to arbitrate among multiple
allowed IRQ requests at the time of an Interrupt Acknowledge access from the CPU.
Write to 01. Write to 01 to write OCW3 (rather than OCW2 or ICW1). (See Section
5.9.2 "PIC Native Registers" on page 339.)
Reserved. Write to 0. (Poll Command at this address is not supported.)
5
(Continued)
initialization.)
PIC_OCW2 Bit Descriptions
PIC_OCW3 Bit Descriptions
PIC_OCW3 Register Map
4
343
01
3
RSVD
2
1
REG_READ
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