cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 80

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

www.national.com
GLPCI_SB Functional Description
4.2.15 Exception Handling
This section describes how various errors are handled by
the PCI Bus Interface block.
Since PERR# is not implemented on the CS5535 or the
GX2 processor, error reporting via this signal is not sup-
ported. In a GX2/CS5535 system, other PCI devices that
do have the PERR# pin must have a pull-up.
4.2.16 Out-Bound Write Exceptions
When performing an out-bound write on PCI, three errors
may occur: master abort, target abort, and parity error.
When a master or target abort occurs, the PCI Bus Inter-
face block will flush any stored write data. If enabled, an
ASMI is generated. ASMI generation is enabled and
reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h).
Parity errors are detected and handled by the processor.
The failed transaction will not be retried.
4.2.17 Out-Bound Read Exceptions
When performing an out-bound read on PCI, three errors
may occur: master abort, target abort, and detected parity
error. When a master or target abort occurs, the PCI Bus
Interface block will return the expected amount of data. If
enabled, an ASMI is generated. ASMI generation is
enabled and reported in GLPCI_SB GLD_MSR_SMI (MSR
51000002h). Parity errors are detected and handled by the
processor. The failed transaction will not be retried.
(Continued)
80
4.2.18 In-Bound Write Exceptions
When performing an in-bound write from PCI, two errors
may occur: a detected parity error and a GLIU exception. A
GLIU exception cannot be relayed back to the originating
PCI bus master, because in-bound PCI writes are always
posted. When a parity error is detected, an ASMI is gener-
ated if it is enabled. ASMI generation is enabled and
reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h).
However, the corrupted write data will be passed along to
the GLIU.
4.2.19 In-Bound Read Exceptions
When performing an in-bound read from the GLIU, the
EXCEP flag may be set on any received bus-WORD of
data. This may be due to an address configuration error
caused by software or by an error reported by the source of
data. The asynchronous ERR and/or SMI bit will be set by
the PCI Bus Interface block and the read data, valid or not,
will be passed to the PCI Bus Interface block along with the
associated exceptions. The PCI Bus Interface block should
simply pass the read response data along to the PCI bus.
Revision 0.8