cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 220

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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GLPCI_SB Register Descriptions
48:43
41:40
39:35
34:32
31:24
23:21
19:18
Bit
42
20
17
Name
RSVD
(RO)
SLTO
ILTO
LAT
0
(RO)
RSVD
(RO)
SUS
RSVD
(RO)
FPIDE
PPIDE
IB/OB
IB/OB
IB/OB
IB/OB
---
IB
IB
---
---
IB
IB
Description
Reserved (Read Only). Returns 0.
Subsequent Latency Time-Out Select. Specifies the subsequent target latency time-
out limit. If, within a burst, the GLPCI_SB module does not respond with the configured
number of clock edges the PCI interface terminates the PCI bus cycle.
0: 8 PCI clock edges.
1: 4 PCI clock edges.
Initial Latency Time-out Select. Specifies the initial target latency time-out limit for the
PCI interface. If the GLPCI_SB module does not respond with the first data phase within
the configured number of clock edges the PCI interface terminates the PCI bus cycle.
00: 32 PCI clock edges.
01: 16 PCI clock edges.
PCI Usage Timer. Usage time-out value for limiting bus tenure.
Constant 0 (Read Only). The three least significant bits of the PCI latency timer field
are fixed as zeros. These bits are not used as part of the PCI latency timer comparison.
Reserved (Read Only). Returns 0.
Busy Sustain. Controls the sustain time for keeping the clocks running after the internal
busy signals indicate that the clocks may be gated.
000: No sustain.
001: 4 clock cycles.
010: 8 clock cycles.
011: 16 clock cycles.
Reserved (Read Only). Returns 0.
Prefetch Primary IDE. If these bits are set, I/O reads to address 1F0h conform to a
prefetching behavior. Under this mode, the GLPCI_SB issues GLIU Read Request
Packets for this specific address before receiving a request on the PCI bus for it. When
IDE prefetch is enabled, all PCI accesses to 1F0h must be DWORDs; that is, 4 bytes.
This setting can only be changed between PIO operations.
00: Off. (Default)
01: At “beginning” initialize pipeline with two read requests.
10: At “beginning” initialize pipeline with three read requests.
11: Reserved.
The prefetch only applies if the current command is "read". The current command is
assumed from the last write to IDE Command Register at 1F7h. The following com-
mands are considered "reads":
Read sectors - 20h
Read multiple - C4h
Read buffer
Prefetch does not cross sector boundaries; that is, 512-byte boundaries. Any prefetched
data is discarded and the “boundary” set to 0 on any write to 1F7h.
Post Primary IDE. Defaults to 0. If this bit is set, I/O writes to address 1F0h are posted;
that is, the “send response” flag is not set in the GLIU Write Request Packet. Effectively,
an I/O write to this specific address is posted just like memory writes are posted. When
IDE posting is enabled, single and double WORD writes may be mixed without restric-
tion.
GLPCI_CTRL Bit Descriptions (Continued)
(Continued)
- E4h
220
10: 8 PCI clock edges.
11: 4 PCI clock edges.
100: 32 clock cycles.
101: 64 clock cycles.
110: 128 clock cycles.
111: 256 clock cycles.
Revision 0.8