cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 151

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
GPIO Subsystem Functional Description
The event counter is based upon a 16-bit programmable
up/down counter. The up-down counter counts positive
edges of the selected GPIO input and produces a constant
or level output when the GPIO_EVNTCNT[x] (counter
value) exceeds the CPIO_EVNTCNT[x]_COMPARE (com-
pare value). The output can be read as the GPIO and/or
used to drive an auxiliary input.
The counter may be counted down one count by writing to
one of two addresses, depending on which bank (High or
Low) the associated GPIO resides in. Knowledge of which
GPIO is associated with the event counter is required,
since these two decrementer registers have a dedicated bit
for each GPIO. When counted down, this counter, unlike
the counter in the digital filter, will roll over from 0000h to
FFFFh. Typically, decrementing is used to clear an interrupt
or power management event as part of the associated ser-
vice routine.
4.15.5.3 Uses of the Event Counter
Such an auxiliary input could be used to drive an ASMI or
maskable interrupt. Assume the compare value is set to 0.
The service routine clears the ASMI by decrementing the
counter via the mechanism illustrated. If additional events
have occurred, the count does not decrement to 0 and the
ASMI remains asserted. The count up and down inputs are
synchronized such that false values are not created if up
and down pulses occur at or near the same instant in time.
The counter will not decrement through 0.
Alternatively, the compare value could be set to a higher
value to trigger an ASMI or interrupt when a certain num-
ber of events has occurred. In this case, the ASMI or inter-
rupt is cleared by writing the counter to 0.
Lastly, the input value may be ignored and the event
counter used as a rate indicator. If software reads the
counter at a fixed periodic interval, an input pulse rate may
be measured. Such an approach may be used to imple-
ment a tachometer function. The counter will increment
past all Fs back to 0.
As suggested above, the counter may be read or written
under software control. The read and write operations are
synchronized such that false values are not created if count
up pulses occur at or near the same instant in time.
4.15.5.4 Input Edge Conditioning Function
The Edge Detection function is illustrated as part of Figure
4-49 on page 149. It is normally used to generate an ASMI
or maskable interrupt on each positive and/or negative
edge of an input signal. Use of this function simultaneously
with the event counter function is somewhat logically mutu-
ally exclusive, but is not prevented in hardware.
Each GPIO has the optional edge detection function.
The reset default for the detection circuit establishes a 0
level
GPIO[x]_NEGEDGE_EN. When both are set to 0, the edge
detection function is disabled. If either a positive or nega-
tive edge detection is enabled, an active high output is pro-
duced when the appropriate edge occurs. This level must
be
cleared
on
by
GPIO[x]_POSEDGE_EN
writing
to
either
and
the
(Continued)
151
GPIO[x]_POSEDGE_STS or the GPIO[x]NEGEDGE_STS
registers, whichever is appropriate. If another edge occurs
before clearing, the active high output is not affected. If the
clear action occurs at the “same time” as another edge, the
result is not defined.
Each edge detection function is controlled by four registers
as follows:
• Positive Edge Enable (GPIO[x]_POSEDGE_EN).
• Negative Edge Enable (GPIO[x]_NEGEDGE_EN).
• Positive Edge Status (GPIO[x]_POSEDGE_STS). Set
• Negative Edge Status (GPIO[x]_POSEDGE_STS). Set
4.15.5.5 Output Steering (Mapping)
Outputs from the internal GPIO circuits, driven by inputs to
the CS5535 from the system, may be steered (or ‘mapped’)
to either interrupts, or power management events (PME).
Sufficient steering logic exists in the CS5535 to provide for
eight independent interrupts and simultaneously for eight
independent PMEs.
The eight GPIO interrupts are all in Working power domain;
of the eight PMEs, [7:6] are in Standby power domain and
[5:0] are in Working domain. Those in the Standby power
domain are intended to be used to awaken the system
when the Working power domain is off, however, they may
also be used when the Working power domain is on. The
interrupts are connected to the PIC subsystem, and the
PMEs are connected to the Power Management sub-
system.
Four 32-bit steering registers control the routing of the
GPIOs’ internal output (that produced by an input to the
chip from an external source, or from one of the internally-
connected AUX inputs) to either an interrupt or PME. The
set of four registers taken together, contain a nibble for
each GPIO. The upper bit of each nibble selects either a
PME (if high) or an interrupt (if low). The remaining three
bits of each nibble select which of the eight possible inter-
rupts or PMEs the GPIO will be steered to.
The four registers are identified as GPIO Mapper X, Y, Z,
and W. Their GPIO associations are as follows:
• GPIO_MAP_X = GPIO[7:0]
• GPIO_MAP_Y = GPIO[15:8]
• GPIO_MAP_Z = GPIO[23:16]
• GPIO_MAP_W = GPIO[31:24]
The steering logic does not prohibit mapping of two or
more GPIOs to the same output, but it is impossible to cre-
ate a single GPIO that functions simultaneously as both an
interrupt and a PME. Registers X, Y, Z, and W default to all
0s, as do both the High and Low EVNT_EN registers.
Thus, all GPIOs are mapped to INT[0] after a reset, but
none are enabled.
Enabled if feature bit is high.
Enabled if feature bit is high.
indicates edge. Write 1 to clear.
indicates edge. Write 1 to clear.
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