cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 217

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
GLPCI_SB Register Descriptions
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:23
15:7
Bit
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Name
RSVD (RO)
TAS_ERR_
FLAG
PARE_ERR_
FLAG
SYSE_ERR_
FLAG
EXCEP_ERR_
FLAG
RSVD (RO)
TAR_ERR_
FLAG
MAR_ERR_
FLAG
RSVD (RO)
TAS_ERR_EN
PARE_ERR_EN
SYSE_ERR_EN
EXCEP_ERR_
EN
RSVD (RO)
TAR_ERR_EN
MAR_ERR_EN
RSVD
Description
Reserved (Read Only). Returns 0.
Target Abort Signaled Error Flag. If high, records that an ERR was generated due to
signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TAS_ERR_EN (bit 6) must be set to enable this event and set flag.
Parity Error Error Flag. If high, records that an ERR was generated due to the detection
of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PARE_ERR_EN (bit 5)
must be set to enable this event and set flag.
System Error Error Flag. If high, records that an ERR was generated due to the detec-
tion of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ERR_EN
(bit 4) must be set to enable this event and set flag.
Exception Bit Error Flag. If high, records that the EXCP bit in the received GLIU read or
write response packet is set. Write 1 to clear. EXCEP_ERR_EN (bit 3) must be set to
enable this event and set flag.
Reserved (Read Only). Returns 0.
Target Abort Received Error Flag. If high, records that an ERR was generated due to
the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TAR_ERR_EN (bit 1) must be set to enable this event and set flag.
Master Abort Received Error Flag. If high, records that an ERR was generated due to
the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
MAR_ERR_EN (bit 0) must be set to enable this event and set flag.
Reserved (Read Only). Returns 0.
Target Abort Signaled Error Enable. Write 1 to enable TAS_ERR_FLAG (bit 22) and to
allow the event to generate an ERR.
Parity Error Error Enable. Write 1 to enable PAR_ERR_FLAG (bit 21) and to allow the
event to generate an ERR.
System Error Error Enable. Write 1 to enable SYSE_ERR_FLAG (bit 20) and to allow
the event to generate an ERR.
Exception Bit Error Enable. Write 1 to enable EXCEP_ERR_FLAG (bit 19) and to allow
the event to generate an ERR.
Reserved (Read Only). Returns 0.
Target Abort Received Error Enable. Write 1 to enable TAR_ERR_FLAG (bit 17) and to
allow the event to generate an ERR.
Master Abort Received Enable. Write 1 to enable MAR_ERR_FLAG (bit 16) and to
allow the event to generate an ERR.
GLPCI_GLD_MSR_ERROR Bit Descriptions
GLPCI_GLD_MSR_ERROR Register Map
(Continued)
RSVD
217
RSVD
9
8
7
6
5
4
3
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2
1
0