cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 71

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
Global Concepts and Features
3.8.4
Each GeodeLink Device within the CS5535 can generate
errors. Furthermore, these errors are controlled via the
Standard
(GLD_MSR_ERROR) located at MSR Address 3 within
each
GLD_MSR_SMI, that is, the lower 32 bits contain Enable
(EN) bits, while the upper 32 bits contain Flag (FLAG) bits
(see Table 3-8 on page 67). The EN and FLAG bits are
organized in pairs of (n, n+32). For example: (0,32); (1,33);
(2,34); etc. The Error MSR is used to control and report
errors.
The SMI concepts of direct asynchronous and synchro-
nous carry over into similar error concepts. However, there
is no concept of an in-direct error. At each GeodeLink
Device, all of the Error FLAG bits are ORed together to
form the Error signal. The Error is routed through the GLIU
where it is ORed with all other device Errors to form the
CS5535 Error signal. This signal is routed to the GLCP for
debug purposes.
Only the GLIU is capable of generating synchronous errors
that utilize the Exception (EXCEP) bit of the associated
response packet. All other CS5535 GeodeLink Devices
only generate asynchronous errors.
3.8.5
All the power management MSRs (GLD_MSR_PM) con-
form to the model illustrated in Table 3-10. The power and
I/O mode functions are completely independent other than
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
MODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Signal
C/BE[3:0]#
DEVSEL#
FRAME#
TRDY#
IRDY#
STOP#
IO
H
Table 3-11. Sleep Driven PCI Signals
GLD.
MSR Address 3: Error Control
MSR Address 4: Power Management
MODE
IO
G
GeodeLink
The
MODE
Ball No.
R6, T9, U11,
U14
R11
U9
T10
R10
T11
IO
F
register
MODE
IO
E
Device
MODE
is
Direction
Pad driven to 0. Internal
logic sees logic 1.
Pad driven to 0. Internal
logic sees logic 1.
Pad driven to 0. Internal
logic sees logic 1.
Pad driven to 0. Internal
logic sees logic 1.
Pad driven to 0. Internal
logic sees logic 1.
Pad driven to 0. Internal
logic sees logic 1.
IO
D
Table 3-10. MSR Power Management Model
organized
MODE
IO
C
Error
(Continued)
MODE
IO
B
just
MSR
MODE
like
IO
A
71
sharing the same MSR. The GLD_MSR_PM fields have
the following definitions:
• Power Mode for Clock Domains:
• I/O Mode (Applies only to GLPCI_SB and ATAC
The PMC controls when the PCI/IDE inputs and outputs
(listed in Table 3-11 and Table 3-12) are asserted and de-
asserted. The PM_OUT_SLPCTL (PMS I/O Offset 0Ch)
and PM_IN_SLPCTL (PMS I/O Offset 20h) registers pro-
vide the global control of the PCI/IDE I/Os. The IO_MODE
bits individually control PCI (GLPCI_SB GLD_MSR_PM
Signal
PAR
REQ#
GNT#
— 00: Disable clock gating. Clocks are always on.
— 01: Enable active hardware clock gating. Clock goes
— 10: Reserved.
— 11: Reserved.
modules, see Table 3-11 and Table 3-12 for a list of
controlled signals):
— 00: No gating of I/O cells during a Sleep sequence
— 01: During a power management Sleep sequence,
— 10: During a power management Sleep sequence,
— 11: Immediately and unconditionally, force inputs to
off whenever this module’s circuits are not busy.
(Default).
force inputs to their non-asserted state when
PM_IN_SLPCTL is enabled.
force inputs to their non-asserted state when
PM_IN_SLPCTL is enabled, and park (force) outputs
low when PM_OUT_SLPCTL is enabled.
their not asserted state, and park (force) outputs low.
Table 3-11. Sleep Driven PCI Signals
Ball No.
U10
T1
R1
9
RSVD
8
7
Direction
Pad driven to 0. Internal
logic sees logic 1.
Pad driven to 0.
Pad TRI-STATE. Internal
logic sees logic 0.
6
5
4
3
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