cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 508

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Flash Controller Register Descriptions
5.19.2.2
Flash Memory Offset Any Even Address between 800h-80Eh
Flash I/O Offset
Type
Reset Value
5.19.2.3
Flash Memory Offset Any Odd Address between 801h-80Fh
Flash I/O Offset
Type
Reset Value
Bit
7:5
Bit
7:0
4
3
2
1
0
7
7
NAND Control Register (NAND_CTL)
NAND I/O (NAND_IO)
Name
RSVD (RO)
DIST_EN
RDY_INT_MASK
ALE
CLE
CE#
Name
IO
RSVD
6
6
04h
R/W
01h
05h
R/W
00h
Description
Reserved (Read Only). Returns 0 when read.
NAND Distract Interrupt Enable.
0: Disables the generation of NAND Distract Interrupt.
1: Enables the generation of NAND Distract Interrupt.
NAND Ready Interrupt Mask.
0: Interrupt is masked.
1: Enable NAND Flash device’s RDY/BUSY# signal to generate an interrupt.
Address Latch Enable. FLASH_ALE output signal reflects the value of this bit.
Command Latch Enable. FLASH_CLE output signal reflects the value of this bit.
Chip Enable. CE# signal reflects the value of this bit. The NAND_CS signals from the
Diverse Device determine which CE# is asserted. Keep this bit low during entire NAND
cycle. Writing a 1 to this bit resets the NAND controller.
Description
I/O Register. Writing to this register triggers a command/address phase sub-cycle on
the NAND Flash interface. The data written to this register is put on the I/O bus during
the sub-cycle. It returns previous written value when read.
Note:
5
5
Before writing to this register check for CTLR_BUSY bit (Flash Memory Offset
810h[2]/Flash I/O Offset 06h[2]) in NAND_STS register to be 0.
NAND_CTL Bit Descriptions
NAND_IO Bit Descriptions
NAND_CTL Register Map
NAND_IO Register Map
DIST_EN
4
4
(Continued)
508
IO
RDY_INT_
MASK
3
3
ALE
2
2
CLE
1
1
CE#
Revision 0.8
0
0