cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 314

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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DIVIL Register Descriptions
If bit 34 = 0; I/O Mapped
If bit 34 = 1; Memory Mapped
63:49
47:36
31:17
63:44
43:35
31:12
15:4
11:0
Bit
3:0
48
35
34
33
32
16
34
33
32
Name
RSVD
RSVD
IO_MASK
RSVD
MEM_IO
NOR_NAND
LBAR_EN
RSVD
RSVD
BASE_ADDR
RSVD
MEM_MASK
RSVD
MEM_IO
NOR_NAND
LBAR_EN
BASE_ADDR
RSVD
Description
Reserved. Reads return value written. Defaults to 0
Reserved. Always write 0.
I/O Address Mask Value. For standard NAND Flash, bits [48:36] should be set to all
1s. Add 0s from the LSBs as needed for OEM specific devices that take more than 16
bytes.See discussion in Section 4.6.1 "LBARs and Comparators" on page 97
Reserved. Reads return value written. Defaults to 0.
Memory or I/O Mapped.
0: LBAR is I/O mapped).
1: LBAR is memory mapped.
NOR or NAND.
0: Use NOR chip select (FLASH_CS[x]#).
1: Use NAND chip select (FLASH_CE[x]#).
LBAR Enable.
0: Disable LBAR.
1: Enable LBAR.
Reserved. Reads return value written. Defaults to 0.
Reserved. Always write 0.
Base Address in I/O Space. See discussion in Section 4.6.1 "LBARs and Compara-
tors" on page 97
Reserved. Reads return value written. Defaults to 0.
Memory Address Mask Value. See discussion in Section 4.6.1 "LBARs and Compar-
ators" on page 97
Reserved. Reads return value written. Defaults to 0.
Memory or I/O Mapped.
0: LBAR is I/O mapped.
1: LBAR is memory mapped.
NOR or NAND.
0: Use NOR chip select (FLASH_CS[x]#).
1: Use NAND chip select (FLASH_CE[x]#).
LBAR Enable.
0: Disable LBAR.
1: Enable LBAR.
Base Address in Memory Space. See discussion in Section 4.6.1 "LBARs and Com-
parators" on page 97
Reserved. Reads return value written. Defaults to 0.
DIVIL_LBAR_FLSH[x] Bit Descriptions
(Continued)
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