cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 183

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
TAP Controller Functional Description
4.20.4 GL_ADDR
This register contains 53 bits for a GeodeLink control
packet and the 17 bits for a GeodeLink data packet. The 17
bits from the data packet are updated if a GeodeLink read
is requested and is available for shifting out. The GL_DATA
description discusses the various conditions under which a
valid request packet is posted to the internal GeodeLink.
Note that since only one GL_ADDR request packet can be
sequenced in with JTAG, the special “read with byte
enable” 2-packet requests that GeodeLink supports cannot
be triggered. Of course, 8, 16, 32, and 64-bit reads can still
be performed and reads of less than 64-bit sizes will gener-
ate the appropriate byte enables at the device. As with
GeodeLink traffic, reads of less than 64 bits must be to an
aligned address, but the data will return in the GL_DATA
adjusted to 64-bit alignment (i.e., a 16-bit read to address
102h should have address bit 1 set and data will return in
bits [31:16] of the 64-bit response). Writes of less than 64
bits must always have 64-bit aligned addresses and should
use the byte enables in the data packet (part of the
GL_ADDR data register) to identify which specific bytes
are to be written.
4.20.5 GL_DATA
The data transfer rate in and out of the JTAG port is limited
to about 90% of the TCK frequency by the GLCP design.
The GLCP is designed for up to 50 MHz TCKs, but typical
TCK rates for industry interfaces are about 15 MHz. As
such, the GLCP JTAG data rate is 14 Mbits/sec or 1.6
Mbytes/sec. Again, however, industry interface boxes will
limit this rate to about 500 kbytes/sec.
GeodeLink requests packets are triggered at these specific
moments:
• If GL_ADDR has been accessed more recently than
• If GL_ADDR_ACT register has been accessed more
Note that if both MSR accesses from the GLIU and JTAG
accesses are interfacing to these registers, the results will
be non-deterministic.
GL_ADDR_ACT and...
— the TYPE of the request is a read and the Update-DR
— the TYPE of the request is a write and the Update-
— the TYPE of the request is a read and the second
recently than GL_ADDR and...
— the GLCP debug logic triggers the GeodeLink_action
JTAG state is entered after loading the GL_ADDR
register.
DR JTAG state is entered after loading the GL_DATA
register.
TCK in the Shift-DR state for shifting out the
GL_DATA register is received and the first two bits
shifted in (GL_DATA DR bits 1 and 0) are non-zero
and the first bit shifted out was non-zero.
due to a debug event occurring.
(Continued)
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4.20.6 PADACC
Provides a test mode whereby USB interface signals or
memory BIST signals can be accessed by input/output
pads. This access is accomplished by writing to the Auxil-
iary Test Register.
4.20.7 PROGMISR
This instruction provides direct access to an MSR used for
the ROM memory BIST test. At the conclusion of the test,
the resulting signature is then checked. A correct test will
result in MBIST_GO being logic-high.
4.20.8 MB_ADDR_ACT
This is the same data register as GL_ADDR, but it disables
any GeodeLink transaction from occurring either on this
access or a following access to the GL_DATA register. Only
the GLCP debug action that triggers a GeodeLink cycle will
cause these bits to be used.
4.20.9 TST_IDDQ
Places the chip in a mode for running IDDQ tests (i.e., gen-
erates an internal signal to disable pull-ups and pull
downs). Also the transceiver is powered off.
4.20.10 REVID
The TAP instruction used to access the current 8-bit revi-
sion code of the chip.
4.20.11 TRISTATE
This instruction will TRI-STATE all of the tri-statable pri-
mary outputs. The DR accessed is the BYPASS register.
4.20.12 BISTDR
Can be used to run all memory BIST controllers in parallel.
4.20.13 IDCODE
This instruction accesses the 32-bit IDCODE register dur-
ing DR access.
4.20.14 BYPASS
In the IEEE 1149.1 specification, shifting all 1s into the IR
must connect the 1-bit BYPASS register. The register has
no function except as a storage flip-flop. This instruction
can also allow relatively easy connection of multiple GLCP
JTAG interface chips. On a board with two GLCP chips,
TMS and TCK of each chip should be wired together and
TDO of one chip should connect to TDI of the other chip.
Note: In parallel scan mode, “input” pads provide data
into the boundary scan cells (the boundary scan
cells provide data into the core). “Cowrie” pads will
behave as dictated by the internal core flops that
normally control the pad; the output data and
enable state will be latched into the boundary scan
cells. “Cheroot” pads will drive out data as dictated
by the internal core flop associated with the pad.
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