cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 165

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PMC Functional Description
4.17.4 PMC Power Management States
The PMC state machines support the fundamental hard-
ware states: Power Off, Reset Standby, Working, Sleep,
and Controlled Standby.
• Reset Standby State: From Power Off, reset is applied
• Working State: The Working state can be entered from
• Sleep State: The system initiates the entry to the Sleep
• Controlled Standby State: Can be entered “normally”,
A normal entry is by way of a system initiated sequence as
in the Sleep case. This method of entry requires the
Standby state machine to monitor SLP_CLK_EN# and look
for an enable of the “Working De-assert Delay and Enable”
register (PM_WKD, PMS I/O Offset 30h[30]) or the
Work_aux
(PM_WKXD, PMS I/O Offset 34h[30]). This signals the
Controlled Standby state normal entry. A Standby wakeup
event returns the system to Working state after a program-
mable delay (PM_NWKD, PMS I/O Offset 4Ch).
If enabled, a faulted entry can be initiated by a low power
off, thermal off, or fail-safe off. It can also be initiated by
Working power fail asserted. A default wakeup event
returns the system to the Working state after a programma-
ble delay (PM_FWKD, PMS I/O Offset 50h).
A re-start can be initiated by any of these resets: GLCP
soft reset, soft reset, shutdown reset, watchdog reset, or
bad packet type reset. The system returns to the Working
state when reset is de-asserted and the faulted_to_work
delay (PM_FWKD) expired. WORKING and WORK_AUX
are not de-asserted.
When a Controlled Standby state is entered by a faulted
condition or restart event, software control is assumed lost
and the software established state is assumed to be poten-
tially wrong. Therefore, the Standby domain returns to the
state associated with “Standby State Entry from Power
Off”; that is, Standby domain reset defaults are used. The
only exceptions are registers from the following list; these
are locked and not subject to change by software:
to the Standby domain by the external input pin
RESET_STAND#. Once reset, the Reset Standby state
de-asserts WORKING and WORK_AUX outputs and
waits for a Reset Standby wakeup event.
Reset Standby, Sleep, or Controlled Standby states.
Working state is established when Working power is
applied and all system clocks are enabled. Once in this
state, registers and functions in the PMC can be initial-
ized, programmed, enabled/disabled, and the potential
exists for the system to proceed to the Sleep state or
Standby state.
state with a Sleep sequence. Under the Sleep state,
Working and Standby power are maintained. PCI/IDE
inputs are disabled when Sleep Acknowledge asserts.
PCI/IDE outputs are disabled when Sleep Acknowledge
asserts or after a programmable delay. SLEEP_X,
SLEEP_Y, and SLP_CLK_EN# may be asserted if
enabled. A Sleep wakeup event returns the system to
Working state.
“fault condition”, or by a “restart”.
De-assert
Delay
and
(Continued)
Enable
register
165
PM_RD
PM_WKXA
PM_FSD
PM_TSD
PM_PSD
PM_NWKD
PM_FWKD
The Faulted to Work Delay and Enable (PM_FWKD) regis-
ter is the only one of the above registers that potentially
applies during a re-start entry.
Lastly, note that any normal entry operation in process is
aborted.
Wakeup from faulted entry is the same as that associated
with Standby State Entry from Power Off; that is, it acts as
if the power button has been pushed. Other possible
wakeup events such as RTC Alarm and PMEs are ignored.
However, the system can be held in the Standby state for
the following reasons:
1)
2)
Note: If enabled and locked, the thermal alarm does not
The Power Management Control (PMC) has two state
machines:
• Working State Machine: Operates under Working
• Standby State Machine: Operates under Standby
power and runs on a 14 MHz clock from the CCU. Its
function is to generate control signals used to turn off/on
systems clocks and I/Os based on events coming from
on or off the chip.
power and runs on the 32 kHz clock. Its function is to
power-up and down the Working power to the Working
domain based on events coming from on or off the chip.
If enabled and locked, the low power indicator is still
asserted.
If LVD_EN# is tied to ground and V
valid voltage, or if RESET_WORK # is asserted.
keep the system in the Standby state if it is
asserted. The thermal alarm circuitry resides in the
Working domain, and its state is ignored by the
Standby state. Once out of Standby, the thermal
alarm again comes into play. If it is still asserted, its
timer would start again.
De-assert Reset Delay from Standby
(PMS I/O Offset 38h)
WORK_AUX Assert Delay from Standby
(PMS I/O Offset 3Ch)
Fail-Safe Delay and Enable
(PMS I/O Offset 40h)
Thermal Safe Delay and Enable
(PMS I/O Offset 44h)
Power Safe Delay and Enable
(PMS I/O Offset 48h)
Normal to Work Delay and Enable
(PMS I/O Offset 4Ch)
Faulted to Work Delay and Enable
(PMS I/O Offset 50h)
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