cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 308

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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DIVIL Register Descriptions
5.6.2.2
MSR Address
Type
Reset Value
See Section 4.6.1 "LBARs and Comparators" on page 97 for operational details.
The KEL registers take 4 kB of memory space. However, only offsets 100h, 104h, 108h, and 10Ch contain registers. All
other writes are “don’t care” and reads return 0.
This is one of two KEL LBARs. Each LBAR “hits” to the same KEL. This allows USB Host Controllers at different addresses
to be used, if desired. Both LBARs do NOT have to be used.
5.6.2.3
MSR Address
Type
Reset Value
See Section 4.6.1 "LBARs and Comparators" on page 97 for operational details.
The KEL registers take 4 kB of memory space. However, only offsets 100h, 104h, 108h, and 10Ch contain registers. All
other writes are “don’t care” and reads return 0.
This is one of two KEL LBARs. Each LBAR "hits" to the same KEL. This allows USB Host Controllers at different addresses
to be used if desired. Both LBARs do NOT have to be used.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:44
43:33
31:12
15:5
11:0
Bit
4:0
Bit
32
Local BAR - KEL from USB Host Controller 1 (DIVIL_LBAR_KEL1)
Local BAR - KEL from USB Host Controller 2 (DIVIL_LBAR_KEL2)
Name
BASE_ADDR
RSVD
Name
MEM_MASK
RSVD
LBAR_EN
BASE_ADDR
RSVD
51400009h
R/W
00000000_00000000h
5140000Ah
R/W
00000000_00000000h
BASE_ADDR
MEM_MASK
Description
Base Address in I/O Space. See discussion in Section 4.6.1 "LBARs and Compara-
tors" on page 97.
Reserved. Reads return 0; writes have no effect.
Description
Memory Address Mask Value. See discussion in Section 4.6.1 "LBARs and Compar-
ators" on page 97
Reserved. Reads return 0; writes have no effect.
LBAR Enable.
0: Disable LBAR.
1: Enable LBAR.
Base Address in Memory Space. See discussion in Section 4.6.1 "LBARs and Com-
parators" on page 97
Reserved. Reads return 0; writes have no effect.
DIVIL_MSR_LBAR_IRQ Bit Descriptions
DIVIL_LBAR_KEL1 Bit Descriptions
(Continued)
DIVIL_LBAR_KEL1 Register Map
308
9
8
7
RSVD
RSVD
6
5
4
3
2
Revision 0.8
1
0