cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 486

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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PMC Register Descriptions
29:22
15:7
Bit
30
21
20
19
18
17
16
6
5
4
3
2
1
0
Name
GPIOM6_PME_
EN
RSVD
GPIOM5_PME_
EN
GPIOM4_PME_
EN
GPIOM3_PME_
EN
GPIOM2_PME_
EN
GPIOM1_PME_
EN
GPIOM0_PME_
EN
RSVD
USBC2_PME_EN
USBC1_PME_EN
UART2_PME_EN
UART1_PME_EN
SMB_PME_EN
PIC_ASMI_PME_
EN
PIC_IRQ_PME_
EN
Description
GPIO IRQ/PME Mapper Bit 6 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 6 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
Reserved. Reads return 0; writes have no effect
GPIO IRQ/PME Mapper Bit 5 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 5 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 4 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 4 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 3 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 3 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 2 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 2 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 1 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 1 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 0 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 0 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
Reserved. Reads return 0; writes have no effect
USB Controller #2 PME Enable. When set high, this bit enables the generation of a
PME to the system if a PME occurs via USB Controller #2. Write this bit low to disable
the generation of a PME from this source.
USB Controller #1PME Enable. When set high, this bit enables the generation of a
PME to the system if a PME occurs via USB Controller #2. Write this bit low to disable
the generation of a PME from this source.
UART #2 PME Enable. When set high, this bit enables the generation of a PME to the
system if a PME occurs via UART #2. Write this bit low to disable the generation of a
PME from this source.
UART #1 PME Enable. When set high, this bit enables the generation of a PME to the
system if a PME occurs via UART #2. Write this bit low to disable the generation of a
PME from this source.
SMB PME Enable. When set high, this bit enables the generation of a PME to the sys-
tem if a PME occurs via the SMB. Write this bit low to disable the generation of a PME
from this source.
PIC ASMI PME Enable. When set high, this bit enables the generation of a PME to the
system if a PME occurs due to a PIC ASMI. Write this bit low to disable the generation
of a PME from this source.
PIC Interrupt PME Enable. When set high, this bit enables the generation of a PME to
the system if a PME occurs due to a PIC Interrupt. Write this bit low to disable the gen-
eration of a PME from this source
PM_GPE0_EN Bit Descriptions (Continued)
(Continued)
486
Revision 0.8