cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 79

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
GLPCI_SB Functional Description
4.2.14 CPU Interface Serial (CIS)
The CIS provides the system interface between the
CS5535 and GX2. The interface supports several modes to
send different combinations of 16-bit side-band signals
through the CIS signal (ball P3). The sideband signals are
synchronized to the PCI clock through 2-stage latching.
Whenever at least one of 16 signals is changed, the serial
transfer (using the PCI clock) immediately starts to send
the information from the South Bridge to the North Bridge.
But, if any bit changes within 20 clocks of any previous
change, the later change will not be transmitted during the
transfer. Another transfer will start immediately after the
conclusion of the transfer due to the subsequent change.
There are three modes of operation for the CIS signal (ball
P3). Note that the transmitted polarity may be different than
the “generally defined” polarity state:
• Mode A - Non-serialized mode with CIS equivalent to
Bit Position
start_0
start_1
data 00
data 01
data 02
data 03
data 04
data 05
data 06
data 07
data 08
data 09
data 10
data 11
data 12
data 13
data 14
data 15
stop_0
stop_1
Note: Mode A is not listed since it is a non-serialized mode with CIS equivalent to SUSP# (reset mode).
SUSP# (reset mode). Not used in normal operation.
Delayed Sleep#
Mode B
Sleep#
SUSP
NMI#
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 4-3. CIS Serial Bits Assignment and Descriptions
Delayed Sleep#
Mode C
Sleep#
ASMI#
INTR#
SUSP
NMI#
0
0
1
1
1
1
1
1
1
1
1
1
1
1
(Continued)
Comment
Start Bit 0
Start Bit 1
Reserved
Reserved
Sleep Request
Non-Maskable Interrupt
Power Management Input Disable
Power Management Output Disable
ASMI or SSMI
Maskable Interrupt out
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Stop Bit 0
Stop Bit 1
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• Mode B - Serialized mode with signals SUSP#, NMI,
• Mode C - Serialized mode with Mode B signals plus
If the GLPCI_MSR_CTRL bit HCD (MSR 51000010h[9]) is
set, any in-bound transaction, except in-bound memory
writes, will be held for any CIS transfer to complete before
claiming completion.
Mode selection is programmed in the GLPCI_MSR_CTRL,
bits [4:3] (MSR 51000010h).
Table 4-3 lists the serial data with corresponding side-band
signals. The serial shift register takes the selected side-
band signals as inputs. The signal SMI is the ORed result
of the SSMI_ASMI_FLAG (SSMI Received Event) bit in
GLPCI_SB GLD_MSR_SMI (MSR 51000002h[18]) and the
side-band signal ASMI. It also serves as a direct output to
the processor.
Sleep, and Delayed Sleep. Not used in normal opera-
tion.
ASMI, and INTR. Used in normal operation.
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