cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 2

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

www.national.com
General Description
The hard disk controller is an ATA-5 compatible bus mas-
tering IDE controller; includes support for two ATA-compli-
ant devices on one channel. Two dual-port USBs (universal
serial buses, USB specification v1.1 compliant) provide
four ports with both low and full-speed capabilities for Plug
& Play expansion for a variety of consumer peripheral
devices such as a keyboard, mouse, printer, and digital
camera. A battery-backed RTC (real-time clock) keeps
track of time and provides calendar functions.
A suite of 82xx devices provide the legacy PC functionality
required by most designs, including two PICs (programma-
ble interrupt controllers), one PIT (programmable interval
timer) with three channels, and DMA (direct memory
access) functions. The CS5535 contains eight MFGPTs
(multi-function general purpose timers) that can be used for
a variety of functions. A number of GPIOs (general purpose
input/outputs) are provided, and are assigned to system
functions on power-up (i.e., LPC port); each of these may
be reassigned and given different I/O characteristics such
as debounce, edge-triggering, etc.
State-of-the-art power management features are attained
with the division of the device into two internal power
domains. The GPIOs and multi-function timers are distrib-
uted into each of the two domains to allow these to act as
wakeup sources for the device. In addition to full ACPI
(Advanced Configuration Power Interface) compliance and
support of industry-standard Wakeup and Sleep modes,
the device automatically disables clocks from internal
blocks when they are not being used.
Features
General Features
GeodeLink PCI Bridge (South Bridge)
Designed for use with National’s Geode GX2 processor
series
208-Terminal PBGA (plastic ball grid array) package
3.3V I/O and 1.5V (nominal) Core operation
Low power operation: less than 1.0W in Working state
Working and Standby power domains
IEEE 1149.1 compliant TAP and boundary scan
Provides a PCI interface for GeodeLink devices:
— PCI specification v2.2 compliant
— 32-Bit, 33/66 MHz operation
— Transaction FIFOs (first in/first out)
— Bus master or slave
— Converts selected PCI configuration bus cycles to
— Capable of handling in-bound transactions immedi-
— Mapping of PCI virtual configuration space to MSR
— Serialized processor control interface
internal MSR (Model Specific Register) cycles
ately after reset - no setup
space is done completely in VSA™ (Virtual System
Architecture
®
) code
(Continued)
2
GeodeLink Control Processor
ATA-5 Controller
Flash Interface
USB Controllers 1 and 2
SUSP#/SUPA# handshake with power management
logic provides Sleep control of all GeodeLink devices
System software debug support using built-in “logic
analyzer” with:
— 8192-bit capture memory
— Capture memory can be organized wide or narrow
— “Analyzer” can be connected to thousands of
— Synchronous operation with GX2 GeodeLink Control
— JTAG interface and system bus interfaces
— For debug use, able to conduct any GeodeLink trans-
— Manufacturing test support
66 MB per second IDE Controller in UDMA mode per
the ATA-5 specification
3.3V interface
Legacy and Enhanced PIO (Programmable I/O),
MDMA (Multi DMA), and UDMA (Ultra DMA) modes
One channel with two devices
Multiplexed with Flash interface
Multiplexed with IDE interface
Connects to array of industry standard NAND Flash
and/or NOR Flash
NOR optional execute-in-place boot source
NAND optional file system
General purpose ISA bus slave-like devices supported
with configurable chip selects
Hardware support for SmartMedia type ECC (Error
Correcting Code) calculation off loading software inten-
sive algorithm
Two independent host USB controllers; doubles the
throughput of a single controller
Each controller has two ports; total of four ports
USB specification v1.1 compliant, with external crimp
protection diodes
OHCI (Open Host Controller Interface) specification v1.0
compliant
Supports wakeup events
Second generation proven core design
Over-current and power control support
GeodeLink master burst reads and writes
possible internal nodes
Processor
action via the JTAG interface
Revision 0.8