cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 35

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
Signal Definitions
2.2.3
The IDE and Flash interface signals are multiplexed together on the same balls as shown in Table 2-7. Section 2.2.3.1 pro-
vides the names and functions of these signals when the interface is in the IDE mode and Section 2.2.3.2 when in Flash
mode (NOR Flash/GPCS and NAND Flash modes).
Note 1.
2.2.3.1
B11, A12
A11
B15, B16, A17, C17,
D16, D17, E17
E16, E15, D15, B17,
C16, C15, A15, B14
C14
B10
C10
B13
C13
A14 (Note 1)
C12
A13
Signal Name
IDE_IRQ0
IDE_RESET#
IDE_AD[2:0]
IDE_DATA[15:0]
Ball No.
IDE/Flash Interface Signals
mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to
keep it high during IDE mode.
Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash
IDE Interface Signals
C17, D16,
C16, C15,
B11, A12,
C14, B15,
B16, A17,
D17, E17,
E16, E15,
D15, B17,
A15, B14
IDE_AD[2:1]
IDE_AD0
IDE_DATA[14:8]
IDE_DATA[7:0]
IDE_DATA15
IDE_CS0#
IDE_CS1#
IDE_IOR0#
IDE_IOW0#
IDE_DREQ0
IDE_DACK0#
IDE_RDY0
Ball No.
(Continued)
B12
F15
A11
IDE Mode
Table 2-7. IDE and Flash Ball Multiplexing
Type
I/O
O
O
I
FLASH_AD[27:26]
FLASH_AD[24:18]
FLASH_AD[17:10]
FLASH_CS2#
FLASH_AD25
FLASH_ALE
FLASH_CS0#
FLASH_CS1#
FLASH_RE#
FLASH_WE#
FLASH_CS3# (Boot Flash Chip Select)
FLASH_IOCHRDY
Description
IDE Interrupt Request Channel 0. This signal is required for all IDE
applications that use IDE DMA modes. It is available on GPIO2, which
must be configured in the AUX_IN mode. If an IDE application will not
use IDE DMA modes, or if the Flash interface will be used instead of
the IDE interface, then this signal may be used as GPIO2.
IDE Reset. An internal reset that is the functional “OR” of inputs
RESET_WORK# and RESET_STAND#. It may also be controlled
directly via an MSR (see Section 5.4.2.2 "Reset Decode
(ATAC_RESET)" on page 254). This signal resets all the devices that
are attached to the IDE interface.
IDE Address Bits. These address bits are used to access a register
or data port in a device on the IDE bus.
IDE Data Lines. IDE_DATA[15:0] transfers data to/from the IDE
devices.
Address Phase
35
NOR Flash/GPCS Mode
FLASH_AD[2:1]
FLASH_AD0
FLASH_AD[9:3]
FLASH_IO[7:0]
Data Phase
---
---
FLASH_IO[7:0]
FLASH_CE0#
FLASH_CE2#
FLASH_CE3#
FLASH_CLE
FLASH_ALE
FLASH_CE1#
FLASH_RE#
FLASH_WE#
FLASH_RDY/BUSY#
NAND Flash Mode
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