cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 432

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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5.16 GPIO SUBSYSTEM REGISTER DESCRIPTIONS
The registers for the General Purpose Input Output (GPIO)
are divided into two sets:
• Standard GeodeLink Device MSRs (Shared with DIVIL,
• GPIO Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 3.2 "CS5535
MSR Addressing" on page 53 for more details on MSR
addressing.
The GPIO Native registers are accessed via a Base
Address Register, MSR_LBAR_GPIO (MSR 5140000Ch),
as I/O Offsets. (See Section 5.6.2.5 on page 310 for bit
descriptions of the Base Address Register.)
The Native registers associated with GPIO configuration
are broadly divided into three categories:
1)
GPIO Low Bank Feature Bit Registers
GPIO I/O
(Note 1)
see Section 5.6.1 on page 299.)
Offset
GPIO Low/High Bank Feature Bit Registers.
These registers (summarized in Table 5-57) control
basic GPIO features. The Feature Bit registers use the
0Ch
1Ch
2Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Table 5-57. GPIO Low/High Bank Feature Bit Registers Summary
Width
(Bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Register Name
GPIO Low Bank Output Value (GPIOL_OUT_VAL)
GPIO Low Bank Output Enable (GPIOL_OUT_EN)
GPIO Low Bank Output Open-Drain Enable
(GPIOL_OUT_OD_EN)
GPIO Low Bank Output Invert Enable
(GPIOL_OUT_INVRT_EN)
GPIO Low Bank Output Auxiliary 1 Select
(GPIOL_OUT_AUX1_SEL)
GPIO Low Bank Output Auxiliary 2 Select
(GPIOL_OUT_AUX2_SEL)
GPIO Low Bank Pull-Up Enable (GPIOL_PU_EN)
GPIO Low Bank Pull-Down Enable (GPIOL_PD_EN)
GPIO Low Bank Input Enable (GPIOL_IN_EN)
GPIO Low Bank Input Invert Enable
(GPIOL_IN_INVRT_EN)
GPIO Low Bank Input Filter Enable
(GPIOL_IN_FLTR_EN)
GPIO Low Bank Input Event Count Enable
(GPIOL_IN_EVNTCNT_EN)
GPIO Low Bank Read Back (GPIOL_READ_BACK)
GPIO Low Bank Input Auxiliary 1 Select
(GPIOL_IN_AUX1_SEL)
GPIO Low Bank Events Enable (GPIOL_EVNT_EN)
432
2)
3)
The reference column in the summary tables point to the
page where the detailed register maps and bit descriptions
are listed. The Low Bank refers to GPIO[15:0] while the
Note: All register bits dealing with GPIO31, GPIO30,
High Bank refers to GPIO[31:16] .
atomic programming model except where noted. See
Section 5.16.1 "Atomic Bit Programming Model" on
page 436 for details.
Input Conditioning Function Registers.
These registers (summarized in Table 5-58 on page
434) are associated with the eight digital filter/event
counter pairs that can be shared with the 32 GPIOs.
These registers are not based on the atomic bit pro-
gramming model.
GPIO Interrupt and PME Mapper Registers.
These registers (summarized in Table 5-59 on page
435) are used for mapping any GPIO to one of the
eight PIC-level interrupts or to one of the eight PME
(Power Management Event) inputs.
GPIO29 and GPIO23 are reserved.
1000EFFFh
EFFF1000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
00000000h
Reset
Value
Reference
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