cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 492

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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PMC Register Descriptions
5.18.3.9
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
5.18.3.10 PM Working De-assert Delay and Enable (PM_WKD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:0
Bit
31
30
PM PCI and IDE Input Sleep Control (PM_IN_SLPCTL)
Name
RSVD
PCI_IDE_IN_SLP
PCI_IDE_IN_SLP
_DELAY
20h
R/W
00000000h
30h
R/W
00000000h
RSVD
Description
Reserved. By convention write 0, but may write anything.
PCI/IDE Input Sleep Control. Allows the delay specified in bits [29:0]
(PCI_IDE_IN_SLP_DELAY) to turn off PCI/IDE inputs as listed in Table 3-11 "Sleep
Driven PCI Signals" and Table 3-12 "Sleep Driven IDE Signals" on page 72. Individual
enables exist for PCI (PCI GLD_MSR_PM, MSR 51000004h[49:48]) and IDE (IDE
GLD_MSR_PM, MSR 51300004h[49:48]).
0: Disable.
1: Enable.
PCI/IDE Input Sleep Control Delay. Indicates the number of 3.57954 MHz clock
edges to wait from Sleep wakeup before PCI/IDE inputs are disabled. Bit 30
(PCI_IDE_IN_SLP) must be high to enable this delay.
(Continued)
PM_IN_SLPCTL Bit Descriptions
PM_IN_SLPCTL Register Map
PM_WKD Register Map
PCI_IDE_IN_SLP_DELAY
492
WORKING_DEASSERT_DELAY
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
Revision 0.8
1
1
0
0