cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 509

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
Flash Controller Register Descriptions
5.19.2.4
Flash Memory Offset 810h
Flash I/O Offset
Type
Reset Value
5.19.2.5
Flash Memory Offset 815h
Flash I/O Offset
Type
Reset Value
Bit
7:4
Bit
7:3
3
2
1
0
7
7
NAND Status (NAND_STS)
NAND ECC Control (NAND_ECC_CTL)
Name
RSVD (RO)
FLASH_RDY (RO)
CTLR_BUSY (RO)
CMD_COMP
DIST_ST
Name
RSVD
6
6
06h
R/W
0xh
08h
R/W
04h
RSVD
Description
Reserved (Read Only). Returns 0 when read.
Flash Ready (Read Only). Double synchronized output (with respect to local bus
clock) of the NAND Flash device’s RDY/BUSY#.
NAND Controller Busy (Read Only). When high, indicates that the NAND Controller’s
state machines are busy.
NAND Command Complete. When high, indicates that the most recent NAND com-
mand has completed. May be read anytime. Write 1 to clear this bit. Writing 0 has no
effect.
NAND Distract Status. Occurrence of a NOR interruption during a NAND transaction
sets this bit. Write 1 to clear this bit. Writing 0 has no effect.
A NAND transaction is started as soon as CE# goes low. It is stopped when CE# goes
high. Typically, a NAND transaction needs multiple software commands (from 6 to
~500). Since the Flash Interface is shared between NAND and NOR Flash Controllers
and the NOR Flash Controller gets priority to use the Flash Interface, a NAND transac-
tion may be interrupted by a NOR transaction. DIST_ST bit is set to record this event.
NAND Flash software must take necessary actions to recover the uncompleted trans-
action.
Description
Reserved. Reads return value written.
RSVD
5
5
NAND_ECC_CTL Bit Descriptions
NAND_ECC_CTL Register Map
NAND_STS Bit Descriptions
NAND_STS Register Map
4
4
(Continued)
509
FLASH_RDY
3
3
CTLR_BUSY
PARITY
2
2
CMD_COMP
CLRECC
1
1
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DIST_ST
ENECC
0
0