cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 316

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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DIVIL Register Descriptions
5.6.2.11
MSR Address
Type
Reset Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
22:20
18:16
15:2
Bit
24
23
19
1
0
Ball Options Control (DIVIL_BALL_OPTS)
Name
LPC_DISABLE_
IO
RSVD
UART2_ENABLE
[2:0]
RSVD
UART1_ENABLE
[2:0]
RSVD
RTC_ENABLE1
RTC_ENABLE0
51400015h
R/W
00000x7xh
Description
LPC Disable I/O. If high, discard all I/O writes which would otherwise go to the LPC by
default. For reads, return all 1s. “Default” means any address not explicitly mapped into
on-chip legacy I/O space or claimed by an LBAR hit.
Reserved. Reads return value written. Defaults to 0.
UART2 Enable.
0xx: UART1 not enabled into DIVIL I/O space; use LPC.
100: UART1 enabled into I/O base 02E8h (COM4).
101: UART1 enabled into I/O base 02F8h (COM3).
110: UART1 enabled into I/O base 03E8h (COM2).
111: UART1 enabled into I/O base 03F8h (COM1).
If UART1 and UART2 are set to the same I/O base, a decode error is generated on
access.
Reserved. Reads return value written. Defaults to 0
UART1 Enable.
0xx: UART1 not enabled into DIVIL I/O space; use LPC.
100: UART1 enabled into I/O base 02E8h (COM4).
101: UART1 enabled into I/O base 02F8h (COM3).
110: UART1 enabled into I/O base 03E8h (COM2).
111: UART1 enabled into I/O base 03F8h (COM1).
If UART1 and UART2 are set to the same I/O base, a decode error is generated on
access.
Reserved. Reads return value written. Defaults to 0
Real-Time Clock Map 1. Routes I/O port locations 072h and 073h to the internal RTC
high RAM or LPC.
0: RTC high RAM routed to LPC bus.
1: RTC high RAM routed to internal RTC. (Default)
Real-Time Clock Map 0. Routes I/O port locations 070h and 071h internal RTC or
LPC. Writes to port 070h (Index) are always routed internal. The MSB is used to estab-
lish the NMI enable state.
0: RTC routed to LPC bus.
1: RTC routed to internal RTC. (Default)
RSVD
DIVIL_LEG_IO Bit Description (Continued)
(Continued)
DIVIL_BALL_OPTS Register Map
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9
8
7
6
5
4
3
2
Revision 0.8
1
0