cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 163

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PMC Functional Description
4.17.3.2 Sleep Controls
Sleep Request/Sleep Acknowledge handshake (see Figure
4-53 on page 161) between the GLCP and PMC controls
the transitions into and out of the Sleep and Standby
states. The PMC starts the Sleep sequence by asserting
Sleep Request to the GLCP. The GLCP requests the pro-
cessor to enter C2 by asserting the SUSP# signal. When
SUSPA# from the processor is received, the GLCP informs
the internal GeodeLink Devices of a pending shutdown and
waits until the GeodeLink Devices’ clock control indicates
that they are ready. The length of time it takes for each
device
51700008h, 51700013h, and 5170000Bh). After all desig-
nated GeodeLink Devices have responded, the GLCP
asserts Sleep Acknowledge to the PMC.
The PM_IN_SLPCTL (PMS I/O Offset 20h) register and the
PM_OUT_SLPCTL (PMS I/O Offset 0Ch) are used to dis-
able PCI/IDE inputs and outputs respectively during Sleep.
Generally, they are asserted at the end of a Sleep
sequence and de-asserted at the beginning of a Wakeup
sequence. When “disabled”, some of the outputs are forced
to TRI-STATE with an active internal pull-down resistor
while the rest are simply pulled low. See Section 3.8.5
"MSR Address 4: Power Management" on page 71 for spe-
cific details on PCI/IDE I/O controls during Sleep.
NOTE: External signals are not necessarily active high. Shown as active high for clarity.
to
Indicates a variable delay.
SLP_CLK_EN# de-asserts at wakeup event and turns on system clocks.
SLEEP_X/SLEEP_Y Controls should de-assert between PCI/IDE input and output controls.
Wakeup sequence begins with a Sleep wakeup event.
respond
is
programmable
Figure 4-55. PMC System Wakeup Sequence
(Continued)
(GLCP
MSR
163
4.17.3.3 Power Controls
In response to Sleep Acknowledge from the GLCP, the
PMC
SLEEP_Y, SLP_CLK_EN#, WORKING, and WORK_AUX.
These can control external electronic power switches and
enables. Each control’s assertion and de-assertion is sub-
ject to an enable and a programmable delay (PMS I/O Off-
set 04h to 3Ch).
Controls SLEEP_X and SLEEP_Y are generic and have no
specific use. Asserting control SLP_CLK_EN# is assumed
to turn off the system (board) clocks. It is always de-
asserted by the wakeup event. The following conditions
apply to the timing of selected output control (see Section
4.17.3.2 "Sleep Controls"), SLEEP_X, SLEEP_Y and
SLP_CLK_EN#.
When going to sleep:
a) If not enabled, SLEEP_X and SLEEP_Y do not assert at
all. If they are enabled, the delay should be set to occur
between the delays programmed in the PM_IN_SLPCTL
and PM_OUT_SLPCTL registers.
b) If SLP_CLK_EN# is enabled, any delays associated with
the PM_OUT_SLPCTL, SLEEP_X, and SLEEP_Y regis-
ters must be less than the SLP_CLK_EN# delay.
c) If SLP_CLK_EN# is enabled, then Sleep wakeup is pos-
sible only after SLP_CLK_EN# asserts.
can
Sleep Request
SUSP#
SUSPA#
GL Device Clock Control
Sleep Acknowledge
PCI/IDE Input Control
SLEEP_X/SLEEP_Y
PCI/IDE Output Control
SLP_CLK_EN#
assert
five
controls/enables:
www.national.com
SLEEP_X,