MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1109

IC MPU 32BIT W/CODE COMP 388PBGA

MPC564CZP40

Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564CZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
1
2
Single Segment Full
Compression
Twin Segments Full
Compression
Twin Segments Full
Compression With
Swapped Vocabularies
(Vocabulary In RAM #2
For MSB Segment)
Left Segment
Compression, Right
Segment Bypassed,
Vocabulary In RAM #1
Left Segment
Compression, Right
Segment Bypassed,
Vocabulary In RAM #2
Left Segment Bypassed,
Right Segment
Compression,
Vocabulary In RAM #1
Left Segment Bypassed,
Right Segment
Compression,
Vocabulary In RAM #2
X1, X2 - pointers to vocabularies
BP - the bypassed data
Configuration
Configu
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
ration
Code
2a
2b
3a
3b
4b
4a
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Table A-4. Instruction Layout Encoding
to RAM
1 and 2
Points
TP1
#
1
1
2
1
2
to RAM
Bypass
Points
TP2
#
2
RAM # Vocab. RAM # Vocab.
TP1BA Points
1
1
1
1
to
V1
V1
V2
V1
V2
TP2BA Points
2
2
2
2
MPC562/MPC564 Compression Features
to
V2
V2
V1
V1
V2
AS DS
0
1
0
1
0
1
0
1
Compressed
Instruction
X1 BP
X1 BP
X2 BP
X2 BP
Layout
X1 X2
X2 X1
X1
1
2
2
2
2
A-21

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