MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 375
![IC MPU 32BIT W/CODE COMP 388PBGA](/photos/39/70/397084/bga-388_sml.jpg)
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.5.7.4
The MPC561/MPC563 can be configured at system reset to use the internal bus arbiter. In this case, the
MPC561/MPC563 will be parked on the bus. The parking feature allows the MPC561/MPC563 to skip the
bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from
the arbiter.
The priority of the external device relative to the internal MPC561/MPC563 bus masters is programmed
in the SIU module configuration register. If the external device requests the bus and the MPC561/MPC563
does not require it, or if the external device has higher priority than the current internal bus master, the
MPC561/MPC563 grants the bus to the external device.
Table 9-4
Freescale Semiconductor
CLKOUT
BR0
BG0
BR1
BG1
BB
and Attributes
TS
TA
ADDR[8:31]
describes the priority mechanism used by the internal arbiter.
Internal Bus Arbiter
Figure 9-26. Bus Arbitration Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
“Turns On” and
Drives Signals
Master 0
(Three-state Controls)
and “Turns Off”
Negates BB
Master 0
“Turns On” and
Drives Signals
Master 1
External Bus Interface
9-35
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