MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 215

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

In order to activate the exception table relocation feature, the following steps are required:
The ETR feature can be activated from reset, by setting corresponding bits in the reset configuration word.
Freescale Semiconductor
.
1. Set the RCPU MSR[IP] bit
2. Set the BBCMCR[ETRE] bit. See
Reserved
System Reset
Machine Check
Reserved
Reserved
External Interrupt
Alignment
Program
Floating Point unavailable
Decrementer
Reserved
Reserved
System Call
Trace
Floating Point Assist
Implementation Dependent
Software Emulation
(BBCMCR),” for programming details.
Name of Exception
The 8 Kbytes allocated for the original PowerPC ISA exception table can be
almost fully utilized. This is possible if the MPC561/MPC563 system
memory is not mapped to the exception address space, (i.e., the addresses
0xFFF0 0000 to 0xFFF0 1FFF are not used).
In such case, these 8 Kbytes can be fully utilized by the compiler, except
for the lower 64 words (256 bytes) which are dedicated for the branch
instructions.
If the RCPU, while executing an exception, issues any address between two
successive exception entries (e.g., 0xFFF0 0104), then the operation of the
MPC561/MPC563 is not guaranteed if the ETR is enabled.
2
Original Address Issues by
Table 4-1. Exception Addresses Mapping
MPC561/MPC563 Reference Manual, Rev. 1.2
0xFFF0 0C00
0xFFF0 0D00
0xFFF0 0A00
0xFFF0 0B00
0xFFF0 0E00
0xFFF0 0000
0xFFF0 0100
0xFFF0 0200
0xFFF0 0300
0xFFF0 0400
0xFFF0 0500
0xFFF0 0600
0xFFF0 0700
0xFFF0 0800
0xFFF0 0900
0xFFF0 1000
Core
Section 4.6.2.1, “BBC Module Configuration Register
NOTE
Compression disabled
Page_Offset
Mapped Address by Exception Table
1
Page_Offset+0x040
Page_Offset+0x000
+0x08
Page_Offset+0x010
Page_Offset+0x018
Page_Offset+0x020
Page_Offset+0x028
Page_Offset+0x030
Page_Offset+0x038
Page_Offset+0x048
Page_Offset+0x050
Page_Offset+0x058
Page_Offset+0x060
Page_Offset+0x068
Page_Offset+0x070
Page_Offset+0x080
Relocation Logic
Burst Buffer Controller 2 Module
Compression enabled
Page_Offset
1
+0x0B8
4-9