MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 259
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Refer to
6.1.7
The time base (TB) is a 64-bit free-running binary counter defined by the MPC500 architecture. The TB
has two independent reference registers which can generate a maskable interrupt when the time base
counter reaches the value programmed in one of the two reference registers. The period of the TB depends
on the driving frequency. The TB is clocked by the TMBCLK clock. The period for the TB is:
The state of TB is not affected by any resets and should be initialized by software. Reads and writes of the
TB are restricted to special instructions. Separate special-purpose registers are defined in the MPC500
architecture for reading and writing the TB. For the MPC561/MPC563 implementation, it is not possible
to read or write the entire TB in a single instruction. Therefore, the mttb and mftb instructions are used to
move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the
upper half (TBU).
Two reference registers are associated with the time base: TBREF0 and TBREF1. A maskable interrupt is
generated when the TB count reaches to the value programmed in one of the two reference registers. Two
status bits in the time base control and status register (TBSCR) indicate which one of the two reference
registers generated the interrupt.
Refer to
Refer to
additional information.
6.1.8
The RTC is a 32-bit counter and pre-divider used to provide a time-of-day indication to the operating
system and application software as show in
Freescale Semiconductor
Section 3.9.5, “Decrementer Register
Section 6.2.2.4, “System Timer
Section 3.9.4, “Time Base Facility (TB) —
Time Base (TB)
Real-Time Clock (RTC)
99
999
9999
999999
9999999
99999999
999999999
(hex) FFFFFFFF
Count Value
Table 6-6. Decrementer Time-Out Periods (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Registers,” for diagrams and bit descriptions of TB registers.
Figure
Time-Out @ 4 MHz
T TB
(DEC),” for more information.
10.0 ms
100.0 s
100 µs
1.0 ms
1000 s
4295 s
10.0 s
=
6-7. It is clocked by the PITRTCLK clock. The counter
1.0 s
----------------------------- -
F TMBCLK
OEA,” and to the RCPU Reference Manual for
2
64
Time-Out @ 20 MHz
200 ms
200 µs
200 s
20 µs
859 s
2 ms
2.0 s
20 s
System Configuration and Protection
6-19
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