MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 852

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Time Processor Unit 3
19.4.13 SIU Test Register (SIUTST)
19.4.14 Factory Test Registers
Table 19-23
also used by TPU debuggers. They can only be used if the TPU is put into its test mode.
19-22
Bits
1:31
SRESET
SRESET
0
Field TPU_DBG
Addr
Field
TPU_DBG
shows registers that are used for factory test only.The TPU Development Support registers are
Name
—
Link Register (LR)
Service Grant Latch Register (SGLR)
Decoded Channel Number Register (DCNR)
Internal Scan Data Register (ISDR)
Internal Scan Control Register (ISCR)
TPU3 Test Configuration Register (TCR)
Development Support Control Register (DSCR)
Development Support Status Register (DSSR)
MSB
16
0
This enables the test features of the TPU for use by TPU debuggers. It should only be enabled
while debugging TPU microcode.
0 TPU debugging is disabled
1 TPU debug is enabled
Reserved, always clear to 0.
17
1
Table 19-23. Registers Used for Factory Test Only
18
2
Figure 19-23. SIUTST — SIU Test Register
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-22. SIUTST Bit Descriptions
Name
19
3
20
4
21
5
0000_0000_0000_0000
0000_0000_0000_0000
22
6
0x2F_C3FC
—
23
7
Description
—
24
8
0x30 402C
0x30 402E
0x30 4022
0x30 4024
0x30 4026
0x30 4002
0x30 4004
0x30 4006
TPU_A
25
9
Address
10
26
11
27
0x30_4404
0x30 442C
0x30 442E
0x30 4422
0x30 4424
0x30 4426
0x30 4402
0x30 4406
TPU_B
12
28
Freescale Semiconductor
13
29
14
30
LSB
15
31