MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1280

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical Characteristics
F.20
All MIOS output pins are slew rate controlled. Slew rate control circuitry adds 90 ns as minimum to the
output timing and 650 ns as a maximum. This slew rate is from 10% V
ns should be added for total 0 to V
Note: After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
Note: VS_PCLK is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and
F.20.1
Note: All delays are in system clock periods.
F-64
1
MCPSM enable to VS_PCLK pulse
PWMSM output resolution
PWM output pulse
Note 1: f
Note 2: The numbers associated with the f
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the
MMCSM) submodules.
The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM
Status/Control Register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not
done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into the
counter.
Prescaler enable
MIOB VS_PCLK
MIOS Timing Characteristics
MMCSM and MPWMSM.
MPWMSM Timing Characteristics
SYS
bit (PREN)
Characteristic
Characteristic
is the internal system clock for the IMB3 bus.
f
SYS
3
Figure F-47. MCPSM Enable to VS_PCLK Pulse Timing Diagram
Table F-24. MPWMSM Timing Characteristics
Table F-23. MCPSM Timing Characteristics
MPC561/MPC563 Reference Manual, Rev. 1.2
1
DD
slew rate.
SYS
Symbol
Symbol
t
t
t
CPSMC
t
PWMO
CPSMC
PWMR
ticks refer to the IMB3 internal state.
(MCPSMSCR_PSL[3:0]) -1
Min
—
2.0
1
Delay
DD
to 90% V
DD
Freescale Semiconductor
, an additional 100
2.0
Max
—
System Clock
2
Cycles
Unit