MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 47

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

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Freescale Semiconductor
Figure
Number
CCW Freeze Situation 17 ..................................................................................................... 13-63
CCW Freeze Situation 18 ..................................................................................................... 13-63
CCW Freeze Situation 19 ..................................................................................................... 13-63
External Trigger Mode (Positive Edge) Timing with Pause................................................. 13-64
Gated Mode, Single-Scan Timing ........................................................................................ 13-65
Gated Mode, Continuous Scan Timing................................................................................. 13-66
Equivalent Analog Input Circuitry ....................................................................................... 13-68
Errors Resulting from Clipping ............................................................................................ 13-69
Star-Ground at the Point of Power Supply Origin ................................................................ 13-71
Electrical Model of an A/D Input Signal .............................................................................. 13-72
External Multiplexing of Analog Signal Sources ................................................................. 13-74
Input Signal Subjected to Negative Stress ............................................................................ 13-76
Input Signal Subjected to Positive Stress ............................................................................. 13-77
QADC64E Block Diagram ..................................................................................................... 14-1
CCW Queue and Result Table Block Diagram ...................................................................... 14-5
Example of External Multiplexing ......................................................................................... 14-6
Module Configuration Register (QADCMCR) ...................................................................... 14-8
QADC Interrupt Register (QADCINT) ................................................................................ 14-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 14-12
Port A Data Register (PORTQA), Port B Data Register (PORTQB)................................... 14-13
Control Register 0 (QACR0) ................................................................................................ 14-14
Control Register 2 (QACR2) ................................................................................................ 14-18
Status Register 0 (QASR0) ................................................................................................... 14-22
Queue Status Transition........................................................................................................ 14-27
Status Register 1 (QASR1) ................................................................................................... 14-28
QADC64E Conversion Queue Operation............................................................................. 14-29
Conversion Command Word Table (CCW) ......................................................................... 14-31
Right Justified, Unsigned Result Format (RJURR).............................................................. 14-35
Left Justified, Signed Result Format (LJSRR) ..................................................................... 14-35
Left Justified, Unsigned Result Register (LJURR) .............................................................. 14-35
QADC64E Analog Subsystem Block Diagram .................................................................... 14-36
Conversion Timing ............................................................................................................... 14-37
QADC64E Queue Operation With Pause ............................................................................. 14-40
QADC64E Clock Subsystem Functions ............................................................................... 14-49
Bus Cycle Accesses .............................................................................................................. 14-52
CCW Priority Situation 1...................................................................................................... 14-55
CCW Priority Situation 2...................................................................................................... 14-55
CCW Priority Situation 3...................................................................................................... 14-56
Port
Control Register 1 (QACR1) ............................................................................................... 14-16
x
Data Direction Register (DDRQA and DDRQB) ...................................................... 14-14
MPC561/MPC563 Reference Manual, Rev. 1.2
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