MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 201

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
3.15.4.14 Implementation-Dependent Instruction Protection Exception (0x1300)
The implementation-specific instruction storage protection error interrupt occurs in the following cases:
The register settings for instruction protection exceptions are shown in
Freescale Semiconductor
1
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
Machine State Register (MSR)
The fetch access violates storage protection and MSR[IR] = 1.
The fetch access is to guarded storage and MSR[IR] = 1.
Register Name
Register Name
Table 3-35. Register Settings following an Instruction Protection Exception
Table 3-34. Register Settings following a Software Emulation Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
DCMPEN
Other
16:31
Other
Bits
Bits
5:15
ME
ME
0:2
LE
LE
All
IP
IP
3
4
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
exception
Set to 1 if the fetch access was to a guarded storage when
MSR[IR] = 1, otherwise clear to 0
Set to 1 if the storage access is not permitted by the protection
mechanism (IMPU in BBC) and MSR[IR] = 1; otherwise clear
to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[IR]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
No change
Cleared to 0
Cleared to 0
No change
Cleared to 0
Description
Description
Table
3-35.
Central Processing Unit
3-57